coreboot-gerrit October 2022

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[M] Change in coreboot[master]: payloads/external/edk2: Add option to clone edk2-paltforms repo
by Michał Żygowski (Code Review) 26 Oct '22

26 Oct '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68872 ) Change subject: payloads/external/edk2: Add option to clone edk2-paltforms repo ...................................................................... payloads/external/edk2: Add option to clone edk2-paltforms repo Add possibility to clone edk2-platforms repository. Some edk2 repositories may use modules from edk2-platforms which contain various feature packages for Intel platforms. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9 --- M payloads/external/Makefile.inc M payloads/external/edk2/Kconfig M payloads/external/edk2/Makefile 3 files changed, 75 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/68872/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 70096f5..dbd2db1 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -165,6 +165,9 @@ CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \ CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \ CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \ + CONFIG_EDK2_USE_EDK2_PLATFORMS=$(CONFIG_EDK2_USE_EDK2_PLATFORMS) \ + CONFIG_EDK2_PLATFORMS_REPOSITORY=$(CONFIG_EDK2_PLATFORMS_REPOSITORY) \ + CONFIG_EDK2_PLATFORMS_TAG_OR_REV=$(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) \ CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \ CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \ CONFIG_EDK2_VERBOSE_BUILD=$(CONFIG_EDK2_VERBOSE_BUILD) \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index e0c19bb..da92274 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -61,6 +61,30 @@ EDK2_REPOSITORY, and in the case of a branch name, prefixed with origin i.e. "origin/uefipayload_202202" +config EDK2_USE_EDK2_PLATFORMS + bool "Use edk2-platforms repository" + default n + help + Clone edk2-platforms repository to the edk2 workspace for additional modules. + +if EDK2_USE_EDK2_PLATFORMS + +config EDK2_PLATFORMS_REPOSITORY + string "URL to git repository for edk2-platforms" + default "https://github.com/tianocore/edk2-platforms" + help + URL to the edk2-platfors repository to clone. + +config EDK2_PLATFORMS_TAG_OR_REV + string "Insert a commit's SHA-1 or a branch name" + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. This must exist in + EDK2_PLATFORMS_REPOSITORY, and in the case of a branch name, prefixed with + origin i.e. "origin/master" + +endif + choice prompt "edk2 build" default EDK2_RELEASE diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 498e11a..1c90ee8 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -6,7 +6,22 @@ project_name = edk2 export WORKSPACE := $(CURDIR)/workspace export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY))) + +ifeq ($(CONFIG_EDK2_USE_EDK2_PLATFORMS),y) +export EDK2_PLATFORMS_PATH := $(WORKSPACE)/edk2-platforms +export PACKAGES_PATH := $(EDK2_PATH):\ + $(EDK2_PLATFORMS_PATH)/Platform/Intel:\ + $(EDK2_PLATFORMS_PATH)/Silicon/Intel:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/Debugging:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/Network:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/OutOfBandManagement:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/PowerManagement:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/SystemInformation:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/UserInterface +else export PACKAGES_PATH := $(EDK2_PATH) +endif ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y) BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc @@ -111,7 +126,24 @@ $(WORKSPACE): mkdir $(WORKSPACE) -$(EDK2_PATH): $(WORKSPACE) +$(EDK2_PLATFORMS_PATH): $(WORKSPACE) + if [ ! -d "$(EDK2_PLATFORMS_PATH)" ]; then \ + git clone --recurse-submodules $(CONFIG_EDK2_PLATFORMS_REPOSITORY) $(EDK2_PLATFORMS_PATH) -j5; \ + fi + cd $(EDK2_PLATFORMS_PATH); \ + if ! git rev-parse --verify -q $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) >/dev/null; then \ + echo " $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) is not a valid git reference"; \ + exit 1; \ + fi; \ + if git status --ignore-submodules=dirty | grep -q clean; then \ + echo " Checking out edk2-platforms revision $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV)"; \ + git checkout --detach $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) -f; \ + else \ + echo " Working directory not clean; will not overwrite"; \ + fi; \ + git submodule update --init --checkout + +$(EDK2_PATH): $(WORKSPACE) $(EDK2_PLATFORMS_PATH) if [ ! -d "$(EDK2_PATH)" ]; then \ git clone --recurse-submodules $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \ fi @@ -168,6 +200,7 @@ echo " ##### $(project_name) Build Summary #####" echo " Repository: $(CONFIG_EDK2_REPOSITORY)" echo " Branch: $(CONFIG_EDK2_TAG_OR_REV)" + echo " Packages path: $(PACKAGES_PATH)" echo " $(BUILD_STR)" | \ sed -e 's/--/-/g' -e 's/-/\n /g' | sort | sed \ -e 's/a /Architecture: /g' \ -- To view, visit https://review.coreboot.org/c/coreboot/+/68872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9 Gerrit-Change-Number: 68872 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
by Arthur Heymans (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68893 ) Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @Kyösti I thought this might help with the e7505 platform where you can't really know how many CPUs you have at runtime from the BSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/68893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f Gerrit-Change-Number: 68893 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 09:26:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
by build bot (Jenkins) (Code Review) 26 Oct '22

26 Oct '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68893 ) Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161391): https://review.coreboot.org/c/coreboot/+/68893/comment/d8bad800_edbe577d PS1, Line 8: Possible repeated word: 'are' File src/cpu/x86/mp_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161391): https://review.coreboot.org/c/coreboot/+/68893/comment/9c66cf55_f84929b2 PS1, Line 490: if (!cpu->enabled) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/68893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f Gerrit-Change-Number: 68893 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Oct 2022 09:24:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
by Arthur Heymans (Code Review) 26 Oct '22

26 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68893 ) Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime ...................................................................... [WIP]cpu/mp_init: Detect the number of CPUs are runtime On some systems the only way to find out what CPUs are are present is by in initializing them and seeing which one checks in. TESTED with qemu reporting a too high number of CPUs. Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c 2 files changed, 63 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/68893/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index bd3be78..3ae16b6 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -27,6 +27,16 @@ with a stub at 0x30000. This is useful on platforms that have an alternative way to set SMBASE. +config X86_UNKNOWN_NUMBER_OF_CPUS + bool + default n + depends on PARALLEL_MP + help + Select this on platforms where the BSP cannot know the number of + lapics that will check except by just launching them all and + seeing who responds. + + config LEGACY_SMP_INIT bool diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 12f0bf6..cf699c0 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -121,7 +121,7 @@ struct mp_flight_record *records; }; -static int global_num_aps; +static volatile int global_num_aps; static struct mp_flight_plan mp_info; static inline void barrier_wait(atomic_t *b) @@ -137,11 +137,11 @@ atomic_set(b, 1); } -static enum cb_err wait_for_aps(atomic_t *val, int target, int total_delay, +static enum cb_err wait_for_aps(atomic_t *val, volatile int *target, int total_delay, int delay_step) { int delayed = 0; - while (atomic_read(val) != target) { + while (atomic_read(val) != *target) { udelay(delay_step); delayed += delay_step; if (delayed >= total_delay) { @@ -466,7 +466,7 @@ return CB_ERR; /* Wait for CPUs to check in up to 200 us. */ - wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); + wait_for_aps(num_aps, &ap_count, 200 /* us */, 15 /* us */); } /* Send final SIPI */ @@ -474,10 +474,25 @@ return CB_ERR; /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */) != CB_SUCCESS) { - printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", + if (wait_for_aps(num_aps, &ap_count, 100000 /* 100 ms */, 50 /* us */) != CB_SUCCESS) { + printk(CONFIG(X86_UNKNOWN_NUMBER_OF_CPUS) ? BIOS_INFO : BIOS_ERR, + "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); - return CB_ERR; + if (!CONFIG(X86_UNKNOWN_NUMBER_OF_CPUS)) + return CB_ERR; + } + + if (CONFIG(X86_UNKNOWN_NUMBER_OF_CPUS)) { + global_num_aps = atomic_read(num_aps); + /* Unlink CPUs from list */ + struct device *prev_cpu = cpu_bus->children; + for (struct device *cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { + if (!cpu->enabled) { + prev_cpu->sibling = cpu->sibling; + } else { + prev_cpu = cpu; + } + } } return CB_SUCCESS; @@ -495,7 +510,6 @@ */ const int timeout_us = MAX(1000000, 100000 * mp_params->num_cpus); const int step_us = 100; - int num_aps = mp_params->num_cpus - 1; struct stopwatch sw; stopwatch_init(&sw); @@ -506,7 +520,7 @@ /* Wait for APs if the record is not released. */ if (atomic_read(&rec->barrier) == 0) { /* Wait for the APs to check in. */ - if (wait_for_aps(&rec->cpus_entered, num_aps, + if (wait_for_aps(&rec->cpus_entered, &global_num_aps, timeout_us, step_us) != CB_SUCCESS) { printk(BIOS_ERR, "MP record %d timeout.\n", i); ret = CB_ERR; @@ -548,6 +562,15 @@ } +struct mp_state { + struct mp_ops ops; + int cpu_count; + uintptr_t perm_smbase; + size_t perm_smsize; + size_t smm_save_state_size; + bool do_smm; +} mp_state; + /* * mp_init() will set up the SIPI vector and bring up the APs according to * mp_params. Each flight record will be executed according to the plan. Note @@ -614,6 +637,8 @@ atomic_read(ap_count), global_num_aps); return CB_ERR; } + p->num_cpus = global_num_aps + 1; + mp_state.cpu_count = p->num_cpus; /* Walk the flight plan for the BSP. */ return bsp_do_flight_plan(p); @@ -659,15 +684,6 @@ spin_unlock(&smm_relocation_lock); } -struct mp_state { - struct mp_ops ops; - int cpu_count; - uintptr_t perm_smbase; - size_t perm_smsize; - size_t smm_save_state_size; - bool do_smm; -} mp_state; - static bool is_smm_enabled(void) { return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm; @@ -1147,6 +1163,10 @@ if (ret == CB_SUCCESS && mp_state.ops.post_mp_init != NULL) mp_state.ops.post_mp_init(); + for (struct device *cpu = cpu_bus->children; cpu; cpu = cpu->sibling) + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f Gerrit-Change-Number: 68893 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/mp_init.c: Only enable CPUs once they execute code
by Arthur Heymans (Code Review) 26 Oct '22

26 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68892 ) Change subject: cpu/mp_init.c: Only enable CPUs once they execute code ...................................................................... cpu/mp_init.c: Only enable CPUs once they execute code On some systems the BSP cannot know how many CPUs are present in the system. A typical use case is a multi socket system. Setting the enable flag only on CPUs that actually exist makes it more flexible. Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/68892/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 2f16db6..12f0bf6 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -195,6 +195,7 @@ /* Fix up APIC id with reality. */ dev->path.apic.apic_id = lapicid(); dev->path.apic.initial_lapicid = initial_lapicid(); + dev->enabled = 1; if (cpu_is_intel()) printk(BIOS_INFO, "AP: slot %zu apic_id %x, MCU rev: 0x%08x\n", info->index, @@ -373,7 +374,7 @@ /* Assuming linear APIC space allocation. AP will set its own APIC id in the ap_init() path above. */ struct device *new = add_cpu_device(cpu_bus, info->cpu->path.apic.apic_id + i, - 1); + 0); if (new == NULL) { printk(BIOS_CRIT, "Could not allocate CPU device\n"); max_cpus--; -- To view, visit https://review.coreboot.org/c/coreboot/+/68892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8 Gerrit-Change-Number: 68892 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/ocp: add VPD processing framework
by Shuming Chu (Shuming) (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Marc Jones, Paul Menzel, Johnny Li, Angel Pons, Tim Chu. Shuming Chu (Shuming) has uploaded a new patch set (#2) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/68784 ) Change subject: drivers/ocp: add VPD processing framework ...................................................................... drivers/ocp: add VPD processing framework Add VPD processing framework to be shared by OCP mainboards: * define VPD configuration items in vpd.h. * add helper functions: ** get_bool_from_vpd() ** get_int_from_vpd_range() Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> --- A src/drivers/ocp/include/vpd.h A src/drivers/ocp/vpd/Kconfig A src/drivers/ocp/vpd/Makefile.inc A src/drivers/ocp/vpd/vpd_util.c 4 files changed, 153 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68784/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Gerrit-Change-Number: 68784 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mainboard/msi/ms7d25: Add support for DDR5 variant
by Michał Żygowski (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Felix Singer, Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68448 ) Change subject: mainboard/msi/ms7d25: Add support for DDR5 variant ...................................................................... Patch Set 3: (1 comment) File src/mainboard/msi/ms7d25/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/68448/comment/b32957fe_4a344ca7 PS2, Line 71: if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) : memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); : if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI)) : memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); > How about adding two additional Kconfig options for DDR4 / DDR5 to the mainboard Kconfig? This scale […] There are actually no more variants of the ms7d25 board. So this will be the last one. Other MSI board will probably have different baseboard codes like ms7dXX something. -- To view, visit https://review.coreboot.org/c/coreboot/+/68448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Gerrit-Change-Number: 68448 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 09:18:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/kano: Add mipi hi556 camera support
by David Wu (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68890 to look at the new patch set (#2). Change subject: mb/google/brya/var/kano: Add mipi hi556 camera support ...................................................................... mb/google/brya/var/kano: Add mipi hi556 camera support This patch supports multiple camera modules based on FW_CONFIG. BUG=b:251235140 TEST=Test the changes with ov2740/hi556 camera. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/68890/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 Gerrit-Change-Number: 68890 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/var/kano: Select camera module based on FW_CONFIG
by David Wu (Code Review) 26 Oct '22

26 Oct '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68890 ) Change subject: mb/google/brya/var/kano: Select camera module based on FW_CONFIG ...................................................................... mb/google/brya/var/kano: Select camera module based on FW_CONFIG This patch supports multiple camera modules, based on FW_CONFIG. BUG=b:251235140 TEST=Test the changes with ov2740/hi556 camera. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/68890/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index c28dd28..fc8dcb3 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -10,6 +10,7 @@ field UFC 4 5 option UFC_USB 0 option UFC_MIPI_OVTI2740 1 + option UFC_MIPI_HI556 2 end field STYLUS 6 option STYLUS_ABSENT 0 @@ -197,6 +198,7 @@ register "cio2_prt[0]" = "1" device generic 0 on probe UFC UFC_MIPI_OVTI2740 + probe UFC UFC_MIPI_HI556 end end end @@ -322,6 +324,45 @@ end end chip drivers/intel/mipi_camera + register "acpi_hid" = ""INT3537"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Hi-556 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "437000000" + register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_C4" #power + register "gpio_panel.gpio[1].gpio_num" = "GPP_F20" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 20 on + probe UFC UFC_MIPI_HI556 + end + end + chip drivers/intel/mipi_camera register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" register "acpi_uid" = "1" register "acpi_name" = ""NVM0"" @@ -336,6 +377,7 @@ device i2c 50 on probe UFC UFC_MIPI_OVTI2740 + probe UFC UFC_MIPI_HI556 end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/68890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 Gerrit-Change-Number: 68890 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in qc_blobs[master]: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes f...
by Bharath N (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Shelley Chen, Julius Werner. Bharath N has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/68889 ) Change subject: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please review -- To view, visit https://review.coreboot.org/c/qc_blobs/+/68889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I3a3bf0f9c6861920e358021332af5f4f8bc7ca71 Gerrit-Change-Number: 68889 Gerrit-PatchSet: 1 Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Saurabh Gorecha <quic_sgorecha(a)quicinc.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Oct 2022 09:00:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022