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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68893 )
Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
@Kyösti I thought this might help with the e7505 platform where you can't really know how many CPUs you have at runtime from the BSP.
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Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161391):
https://review.coreboot.org/c/coreboot/+/68893/comment/d8bad800_edbe577d
PS1, Line 8:
Possible repeated word: 'are'
File src/cpu/x86/mp_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161391):
https://review.coreboot.org/c/coreboot/+/68893/comment/9c66cf55_f84929b2
PS1, Line 490: if (!cpu->enabled) {
braces {} are not necessary for any arm of this statement
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68893 )
Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
......................................................................
[WIP]cpu/mp_init: Detect the number of CPUs are runtime
On some systems the only way to find out what CPUs are are present is by
in initializing them and seeing which one checks in.
TESTED with qemu reporting a too high number of CPUs.
Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/Kconfig
M src/cpu/x86/mp_init.c
2 files changed, 63 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/68893/1
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index bd3be78..3ae16b6 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -27,6 +27,16 @@
with a stub at 0x30000. This is useful on platforms that have
an alternative way to set SMBASE.
+config X86_UNKNOWN_NUMBER_OF_CPUS
+ bool
+ default n
+ depends on PARALLEL_MP
+ help
+ Select this on platforms where the BSP cannot know the number of
+ lapics that will check except by just launching them all and
+ seeing who responds.
+
+
config LEGACY_SMP_INIT
bool
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 12f0bf6..cf699c0 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -121,7 +121,7 @@
struct mp_flight_record *records;
};
-static int global_num_aps;
+static volatile int global_num_aps;
static struct mp_flight_plan mp_info;
static inline void barrier_wait(atomic_t *b)
@@ -137,11 +137,11 @@
atomic_set(b, 1);
}
-static enum cb_err wait_for_aps(atomic_t *val, int target, int total_delay,
+static enum cb_err wait_for_aps(atomic_t *val, volatile int *target, int total_delay,
int delay_step)
{
int delayed = 0;
- while (atomic_read(val) != target) {
+ while (atomic_read(val) != *target) {
udelay(delay_step);
delayed += delay_step;
if (delayed >= total_delay) {
@@ -466,7 +466,7 @@
return CB_ERR;
/* Wait for CPUs to check in up to 200 us. */
- wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */);
+ wait_for_aps(num_aps, &ap_count, 200 /* us */, 15 /* us */);
}
/* Send final SIPI */
@@ -474,10 +474,25 @@
return CB_ERR;
/* Wait for CPUs to check in. */
- if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */) != CB_SUCCESS) {
- printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n",
+ if (wait_for_aps(num_aps, &ap_count, 100000 /* 100 ms */, 50 /* us */) != CB_SUCCESS) {
+ printk(CONFIG(X86_UNKNOWN_NUMBER_OF_CPUS) ? BIOS_INFO : BIOS_ERR,
+ "Not all APs checked in: %d/%d.\n",
atomic_read(num_aps), ap_count);
- return CB_ERR;
+ if (!CONFIG(X86_UNKNOWN_NUMBER_OF_CPUS))
+ return CB_ERR;
+ }
+
+ if (CONFIG(X86_UNKNOWN_NUMBER_OF_CPUS)) {
+ global_num_aps = atomic_read(num_aps);
+ /* Unlink CPUs from list */
+ struct device *prev_cpu = cpu_bus->children;
+ for (struct device *cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
+ if (!cpu->enabled) {
+ prev_cpu->sibling = cpu->sibling;
+ } else {
+ prev_cpu = cpu;
+ }
+ }
}
return CB_SUCCESS;
@@ -495,7 +510,6 @@
*/
const int timeout_us = MAX(1000000, 100000 * mp_params->num_cpus);
const int step_us = 100;
- int num_aps = mp_params->num_cpus - 1;
struct stopwatch sw;
stopwatch_init(&sw);
@@ -506,7 +520,7 @@
/* Wait for APs if the record is not released. */
if (atomic_read(&rec->barrier) == 0) {
/* Wait for the APs to check in. */
- if (wait_for_aps(&rec->cpus_entered, num_aps,
+ if (wait_for_aps(&rec->cpus_entered, &global_num_aps,
timeout_us, step_us) != CB_SUCCESS) {
printk(BIOS_ERR, "MP record %d timeout.\n", i);
ret = CB_ERR;
@@ -548,6 +562,15 @@
}
+struct mp_state {
+ struct mp_ops ops;
+ int cpu_count;
+ uintptr_t perm_smbase;
+ size_t perm_smsize;
+ size_t smm_save_state_size;
+ bool do_smm;
+} mp_state;
+
/*
* mp_init() will set up the SIPI vector and bring up the APs according to
* mp_params. Each flight record will be executed according to the plan. Note
@@ -614,6 +637,8 @@
atomic_read(ap_count), global_num_aps);
return CB_ERR;
}
+ p->num_cpus = global_num_aps + 1;
+ mp_state.cpu_count = p->num_cpus;
/* Walk the flight plan for the BSP. */
return bsp_do_flight_plan(p);
@@ -659,15 +684,6 @@
spin_unlock(&smm_relocation_lock);
}
-struct mp_state {
- struct mp_ops ops;
- int cpu_count;
- uintptr_t perm_smbase;
- size_t perm_smsize;
- size_t smm_save_state_size;
- bool do_smm;
-} mp_state;
-
static bool is_smm_enabled(void)
{
return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm;
@@ -1147,6 +1163,10 @@
if (ret == CB_SUCCESS && mp_state.ops.post_mp_init != NULL)
mp_state.ops.post_mp_init();
+ for (struct device *cpu = cpu_bus->children; cpu; cpu = cpu->sibling)
+ printk(BIOS_DEBUG, "CPU: %s %s\n",
+ dev_path(cpu), cpu->enabled?"enabled":"disabled");
+
return ret;
}
--
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68892 )
Change subject: cpu/mp_init.c: Only enable CPUs once they execute code
......................................................................
cpu/mp_init.c: Only enable CPUs once they execute code
On some systems the BSP cannot know how many CPUs are present in the
system. A typical use case is a multi socket system. Setting the enable
flag only on CPUs that actually exist makes it more flexible.
Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/mp_init.c
1 file changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/68892/1
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 2f16db6..12f0bf6 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -195,6 +195,7 @@
/* Fix up APIC id with reality. */
dev->path.apic.apic_id = lapicid();
dev->path.apic.initial_lapicid = initial_lapicid();
+ dev->enabled = 1;
if (cpu_is_intel())
printk(BIOS_INFO, "AP: slot %zu apic_id %x, MCU rev: 0x%08x\n", info->index,
@@ -373,7 +374,7 @@
/* Assuming linear APIC space allocation. AP will set its own
APIC id in the ap_init() path above. */
struct device *new = add_cpu_device(cpu_bus, info->cpu->path.apic.apic_id + i,
- 1);
+ 0);
if (new == NULL) {
printk(BIOS_CRIT, "Could not allocate CPU device\n");
max_cpus--;
--
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Shuming Chu (Shuming) has uploaded a new patch set (#2) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/68784 )
Change subject: drivers/ocp: add VPD processing framework
......................................................................
drivers/ocp: add VPD processing framework
Add VPD processing framework to be shared by OCP mainboards:
* define VPD configuration items in vpd.h.
* add helper functions:
** get_bool_from_vpd()
** get_int_from_vpd_range()
Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com>
---
A src/drivers/ocp/include/vpd.h
A src/drivers/ocp/vpd/Kconfig
A src/drivers/ocp/vpd/Makefile.inc
A src/drivers/ocp/vpd/vpd_util.c
4 files changed, 153 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68784/2
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68448 )
Change subject: mainboard/msi/ms7d25: Add support for DDR5 variant
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/msi/ms7d25/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/68448/comment/b32957fe_4a344ca7
PS2, Line 71: if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4))
: memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false);
: if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI))
: memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false);
> How about adding two additional Kconfig options for DDR4 / DDR5 to the mainboard Kconfig? This scale […]
There are actually no more variants of the ms7d25 board. So this will be the last one. Other MSI board will probably have different baseboard codes like ms7dXX something.
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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68890
to look at the new patch set (#2).
Change subject: mb/google/brya/var/kano: Add mipi hi556 camera support
......................................................................
mb/google/brya/var/kano: Add mipi hi556 camera support
This patch supports multiple camera modules based on FW_CONFIG.
BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689
---
M src/mainboard/google/brya/variants/kano/overridetree.cb
1 file changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/68890/2
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Bharath N has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/68889 )
Change subject: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Please review
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