coreboot-gerrit October 2022

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[L] Change in coreboot[master]: [WIP] security/tpm: add TPM log format as per 1.2 spec
by Sergii Dmytruk (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Sergii Dmytruk. Hello build bot (Jenkins), Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68747 to look at the new patch set (#3). Change subject: [WIP] security/tpm: add TPM log format as per 1.2 spec ...................................................................... [WIP] security/tpm: add TPM log format as per 1.2 spec Used by default for all boards with TPM1 which don't specify log format explicitly. Ticket: https://ticket.coreboot.org/issues/423 Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc A src/security/tpm/tpm12_log_serialized.h M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h A src/security/tpm/tspi/log-tpm12.c 7 files changed, 266 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/68747/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Gerrit-Change-Number: 68747 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: [WIP] security/tpm: improve tlcl_extend() signature
by Sergii Dmytruk (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Erik van den Bogaert, Michał Żygowski, Maciej Pijanowski, Frans Hendriks, Christian Walter, Sergii Dmytruk. Hello Erik van den Bogaert, build bot (Jenkins), Michał Żygowski, Maciej Pijanowski, Frans Hendriks, Christian Walter, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68745 to look at the new patch set (#3). Change subject: [WIP] security/tpm: improve tlcl_extend() signature ...................................................................... [WIP] security/tpm: improve tlcl_extend() signature Until now tcg-2.0/tss.c was just assuming certain buffer size and hash algorithm. Change it to accept digest type, which the call sites know. Also drop `uint8_t *out_digest` parameter which was always `NULL` and was handled only by tcg-1.2 code. Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c M src/vendorcode/eltan/security/mboot/mboot.c 6 files changed, 59 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/68745/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Gerrit-Change-Number: 68745 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68866 ) Change subject: soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE ...................................................................... soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE Currently the GPP clk req configuration code assumes that the size of the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that code to use the `ARRAY_SIZE` macro instead. BRANCH=guybrush BUG=b:250009974 TEST=Ran on nipperkin device, verified that clk req settings are correct. Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/fch.c 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 7227d20..1ceb8bc 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -153,7 +153,8 @@ uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); -- To view, visit https://review.coreboot.org/c/coreboot/+/68866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7 Gerrit-Change-Number: 68866 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/cezanne: Factor out common GPP clk req code
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68138 ) Change subject: soc/amd/cezanne: Factor out common GPP clk req code ...................................................................... soc/amd/cezanne: Factor out common GPP clk req code Factor out the `gpp_dxio_update_clk_req_config` function as it will be useful for other AMD SoCs. BUG=b:250009974 TEST=Ran on nipperkin device, verified clk req settings match enabled devices Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c A src/soc/amd/common/block/include/amdblocks/pci_clk_req.h M src/soc/amd/common/block/pci/Kconfig M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/pcie_clk_req.c 7 files changed, 146 insertions(+), 94 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index b8209f8..546ea20 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -58,6 +58,7 @@ select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER + select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 00eb560..a8b7f22 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -5,6 +5,7 @@ #include <amdblocks/chip.h> #include <amdblocks/i2c.h> +#include <amdblocks/pci_clk_req.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -12,12 +13,6 @@ #include <types.h> #include <vendorcode/amd/fsp/cezanne/FspUsb.h> -enum gpp_clk_req { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ -}; - struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index b791037..7227d20 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -3,6 +3,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/pci_clk_req.h> #include <amdblocks/gpio.h> #include <amdblocks/i2c.h> #include <amdblocks/smi.h> @@ -134,93 +135,6 @@ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); } -/* Update gpp glk req config based on DXIO descriptors and enabled devices. */ -static void gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, - size_t gpp_clk_config_num) -{ - const fsp_dxio_descriptor *dxio_descs = NULL; - const fsp_ddi_descriptor *ddi_descs = NULL; - size_t dxio_num = 0; - size_t ddi_num = 0; - - mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num); - if (dxio_descs == NULL) { - printk(BIOS_WARNING, - "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n"); - return; - } - - for (int i = 0; i < dxio_num; i++) { - const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i]; - - /* Only consider PCIe and unused engine types. */ - if (dxio_desc->engine_type != PCIE_ENGINE - && dxio_desc->engine_type != UNUSED_ENGINE) - continue; - enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req; - - /* CLK_DISABLE means there's no corresponding clk req line in use */ - if (dxio_clk_req == CLK_DISABLE) - continue; - - /* - * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for - * a descriptor should cause a compiler error. 0xF isn't a - * valid clk_req value according to AMD's internal code either. - * This is here to draw attention in case this code is ever used - * in a situation where this has changed. - */ - if (dxio_clk_req == (CLK_ENABLE & 0xF)) { - printk(BIOS_WARNING, - "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i); - continue; - } - - /* cpm_clk_req 0 is CLK_DISABLE */ - int gpp_req_index = dxio_clk_req - CLK_REQ0; - /* Ensure that our index is valid */ - if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) { - printk(BIOS_ERR, "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n", - dxio_clk_req, dxio_desc->device_number, - dxio_desc->function_number, i); - continue; - } - - const struct device *pci_device = pcidev_path_on_root( - PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number)); - if (pci_device == NULL) { - gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; - printk(BIOS_WARNING, - "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i, - gpp_req_index); - continue; - } - - /* PCIe devices haven't been fully set up yet, so directly read the vendor id - * and device id to determine if a device is physically present. If a device - * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000, - * and 0x0000ffff are there to account for any odd failure cases. */ - u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID); - bool enabled = pci_device->enabled && (id != 0xffffffff) && - (id != 0x00000000) && (id != 0x0000ffff) && (id != 0xffff0000); - - /* Inform of possible mismatches between devices and SoC gpp_clk_config. */ - if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) { - gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; - printk(BIOS_INFO, - "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, - gpp_req_index, i); - } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) { - printk(BIOS_INFO, - "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i); - } - } -} - /* Configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -239,7 +153,7 @@ uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); diff --git a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h new file mode 100644 index 0000000..32dadf4 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_PCI_GPP_H +#define AMD_BLOCK_PCI_GPP_H + +#include <soc/platform_descriptors.h> + +enum gpp_clk_req { + GPP_CLK_ON, /* GPP clock always on; default */ + GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ + GPP_CLK_OFF, /* GPP clk off */ +}; + +void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, + size_t gpp_clk_config_num); + +#endif diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 302a6b8..1c21833 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -16,3 +16,10 @@ depends on SOC_AMD_COMMON_BLOCK_PCI help Select this option to use AMD common PCIe GPP driver. + +config SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ + bool + depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER + help + This option includes code to disable PCIe clock request if the corresponding + PCIe device is disabled. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index e013777..03958c7 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -4,6 +4,7 @@ ramstage-y += pci_routing_info.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ) += pcie_clk_req.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/common/block/pci/pcie_clk_req.c b/src/soc/amd/common/block/pci/pcie_clk_req.c new file mode 100644 index 0000000..881c650 --- /dev/null +++ b/src/soc/amd/common/block/pci/pcie_clk_req.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/pci_clk_req.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/platform_descriptors.h> + +/* Update gpp glk req config based on DXIO descriptors and enabled devices. */ +void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, + size_t gpp_clk_config_num) +{ + const fsp_dxio_descriptor *dxio_descs = NULL; + const fsp_ddi_descriptor *ddi_descs = NULL; + size_t dxio_num = 0; + size_t ddi_num = 0; + + mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num); + if (dxio_descs == NULL) { + printk(BIOS_WARNING, + "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n"); + return; + } + + for (int i = 0; i < dxio_num; i++) { + const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i]; + + /* Only consider PCIe and unused engine types. */ + if (dxio_desc->engine_type != PCIE_ENGINE + && dxio_desc->engine_type != UNUSED_ENGINE) + continue; + enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req; + + /* CLK_DISABLE means there's no corresponding clk req line in use */ + if (dxio_clk_req == CLK_DISABLE) + continue; + + /* + * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for + * a descriptor should cause a compiler error. 0xF isn't a + * valid clk_req value according to AMD's internal code either. + * This is here to draw attention in case this code is ever used + * in a situation where this has changed. + */ + if (dxio_clk_req == (CLK_ENABLE & 0xF)) { + printk(BIOS_WARNING, + "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i); + continue; + } + + /* cpm_clk_req 0 is CLK_DISABLE */ + int gpp_req_index = dxio_clk_req - CLK_REQ0; + /* Ensure that our index is valid */ + if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) { + printk(BIOS_ERR, + "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n", + dxio_clk_req, dxio_desc->device_number, + dxio_desc->function_number, i); + continue; + } + + const struct device *pci_device = pcidev_path_on_root( + PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number)); + if (pci_device == NULL) { + gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; + printk(BIOS_WARNING, + "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i, + gpp_req_index); + continue; + } + + /* PCIe devices haven't been fully set up yet, so directly read the vendor id + * and device id to determine if a device is physically present. If a device + * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000, + * and 0x0000ffff are there to account for any odd failure cases. */ + u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID); + bool enabled = pci_device->enabled && (id != 0xffffffff) && (id != 0x00000000) + && (id != 0x0000ffff) && (id != 0xffff0000); + + /* Inform of possible mismatches between devices and SoC gpp_clk_config. */ + if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) { + gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; + printk(BIOS_INFO, + "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, + gpp_req_index, i); + } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) { + printk(BIOS_INFO, + "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Gerrit-Change-Number: 68138 Gerrit-PatchSet: 9 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/cezanne: Factor out common GPP clk req code
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68138 ) Change subject: soc/amd/cezanne: Factor out common GPP clk req code ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/common/block/pci/Kconfig: https://review.coreboot.org/c/coreboot/+/68138/comment/baad8e9c_bfd41eb4 PS6, Line 16: depends on SOC_AMD_COMMON_BLOCK_PCI > Unfortunately not as is. Prior to Cezanne platform_descriptors. […] maybe the pcie gpp clock fixup code can/should also be used on picasso, but that's something for some future cleanup patch. right now selecting this from each socs config should be the way to go -- To view, visit https://review.coreboot.org/c/coreboot/+/68138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Gerrit-Change-Number: 68138 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 22:01:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel/common: Fix typecasting issue
by Angel Pons (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Gaggery Tsai, Kedar J. Karanje, Sridhar Siricilla, Arthur Heymans, Kane Chen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68899 ) Change subject: cpu/intel/common: Fix typecasting issue ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35d382c792b9df260381b7696f3bbff43d6c4dc2 Gerrit-Change-Number: 68899 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 21:55:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Use detect vs probed flag for touchscreens
by Matt DeVillier (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Frank Wu, Jason Nien, Martin Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67779 ) Change subject: mb/google/skyrim: Use detect vs probed flag for touchscreens ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Hi Matt, […] hi Frank, this CL depends on CB:67779, but I will update/rebase and include frostflow's override tree in this patch as well -- To view, visit https://review.coreboot.org/c/coreboot/+/67779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f Gerrit-Change-Number: 67779 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 21:17:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
by Tim Van Patten (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, EricKY Cheng, Matt DeVillier, Chris Wang, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68469 ) Change subject: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles ...................................................................... Patch Set 8: (2 comments) File src/soc/amd/mendocino/chip.h: https://review.coreboot.org/c/coreboot/+/68469/comment/629d522f_f43528e5 PS8, Line 81: uint32_t thermctl_limit_degreeC_B; Looking at the table in https://b.corp.google.com/issues/232946420#comment116, `Thermctl Limit(APU)` is the same as table A for every case, so it can be removed for the rest of the tables (B/C/etc profile). https://review.coreboot.org/c/coreboot/+/68469/comment/737b1846_456241d6 PS8, Line 88: uint16_t stt_alpha_apu_B; : uint16_t stt_error_coeff_B; : uint16_t stt_error_rate_coefficient_B; Looking at the table in https://b.corp.google.com/issues/232946420#comment116, these 3 values are the same as table A for every case, so they can be removed for the rest of the tables (B/C/etc profile). -- To view, visit https://review.coreboot.org/c/coreboot/+/68469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Gerrit-Change-Number: 68469 Gerrit-PatchSet: 8 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 21:16:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable DPTC support
by Tim Van Patten (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Jason Nein, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68076 ) Change subject: mb/google/skyrim/var/winterhold: Enable DPTC support ...................................................................... Patch Set 5: -Code-Review (1 comment) File src/mainboard/google/skyrim/Kconfig.name: https://review.coreboot.org/c/coreboot/+/68076/comment/55b6c433_472607cd PS5, Line 6: select SOC_AMD_COMMON_BLOCK_ACPI_DPTC `src/mainboard/google/skyrim/Kconfig` needs to be updated also, to remove: ``` select SOC_AMD_COMMON_BLOCK_ACPI_DPTC if !BOARD_GOOGLE_WINTERHOLD && !BOARD_GOOGLE_MORTHAL ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/68076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97c2d3ee29687cd8a9c459e90a45cef05ac4436b Gerrit-Change-Number: 68076 Gerrit-PatchSet: 5 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nein <finaljason(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Jason Nein <finaljason(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Oct 2022 21:09:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update touchscreen devicetree setting
by Tim Van Patten (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Martin Roth, Eric Peers, Karthikeyan Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68741 ) Change subject: mb/google/skyrim/var/winterhold: Update touchscreen devicetree setting ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68741/comment/60806b31_46ea34ab PS1, Line 14: TEST=emerge-skyrim coreboot Please indicate what testing has been done, beyond just building with the CL. Does the touchscreen work correctly now, whereas it didn't before? -- To view, visit https://review.coreboot.org/c/coreboot/+/68741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568346d2abc39d9427e49c3b21f38db0184b8b44 Gerrit-Change-Number: 68741 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Oct 2022 21:07:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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