coreboot-gerrit October 2022

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[M] Change in coreboot[master]: mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generation
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68849 ) Change subject: mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generation ...................................................................... mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generation This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Bilby, Birman, Chausie and Majolica. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/birman/mainboard.c M src/mainboard/amd/chausie/mainboard.c M src/mainboard/amd/majolica/mainboard.c 4 files changed, 101 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index c594a90..ca85684 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -56,18 +56,32 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + static void init_tables(void) { - const struct fch_irq_routing *entry; - int i; + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - for (i = 0; i < ARRAY_SIZE(fch_irq_map); i++) { - entry = fch_irq_map + i; - fch_pic_routing[entry->intr_index] = entry->pic_irq_num; - fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; } } diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c index 4c641f5..28c289d 100644 --- a/src/mainboard/amd/birman/mainboard.c +++ b/src/mainboard/amd/birman/mainboard.c @@ -2,6 +2,7 @@ #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> +#include <console/console.h> #include <device/device.h> #include <soc/acpi.h> #include <string.h> @@ -60,18 +61,32 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + static void init_tables(void) { - const struct fch_irq_routing *entry; - int i; + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - for (i = 0; i < ARRAY_SIZE(fch_irq_map); i++) { - entry = fch_irq_map + i; - fch_pic_routing[entry->intr_index] = entry->pic_irq_num; - fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; } } diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c index c014236..9515f24 100644 --- a/src/mainboard/amd/chausie/mainboard.c +++ b/src/mainboard/amd/chausie/mainboard.c @@ -2,6 +2,7 @@ #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> +#include <console/console.h> #include <device/device.h> #include <soc/acpi.h> #include <string.h> @@ -58,18 +59,32 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + static void init_tables(void) { - const struct fch_irq_routing *entry; - int i; + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - for (i = 0; i < ARRAY_SIZE(fch_irq_map); i++) { - entry = fch_irq_map + i; - fch_pic_routing[entry->intr_index] = entry->pic_irq_num; - fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; } } diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index 31ac515..a5e2935 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -2,6 +2,7 @@ #include <amdblocks/amd_pci_util.h> #include <commonlib/helpers.h> +#include <console/console.h> #include <device/device.h> #include <soc/acpi.h> #include <string.h> @@ -58,18 +59,32 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + static void init_tables(void) { - const struct fch_irq_routing *entry; - int i; + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - for (i = 0; i < ARRAY_SIZE(fch_irq_map); i++) { - entry = fch_irq_map + i; - fch_pic_routing[entry->intr_index] = entry->pic_irq_num; - fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Gerrit-Change-Number: 68849 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/asus/p5qc: Add ASUS P5Q-E as a variant
by Stefan Ott (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Name of user not set #1004033. Stefan Ott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60011 ) Change subject: mb/asus/p5qc: Add ASUS P5Q-E as a variant ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: While I cannot say anything about the P5Q-E, this does not appear to negatively affect the P5Q. -- To view, visit https://review.coreboot.org/c/coreboot/+/60011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8415fe88a421c529308279381aa62e2160e171 Gerrit-Change-Number: 60011 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1004033 Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1004033 Gerrit-Comment-Date: Wed, 26 Oct 2022 23:06:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
by Tim Van Patten (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Jason Glenesk, EricKY Cheng, Matt DeVillier, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal ...................................................................... Patch Set 12: (2 comments) File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/8177ae47_dc9af3f8 PS10, Line 44: //over 50 > This implementation isn't quite correct. Imagine the following scenario: […] After chatting with Raul, he pointed out that storing the previously applied table ID in a `Name`d object should work, rather than re-purposing the DPTF shared memory. See: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… https://review.coreboot.org/c/coreboot/+/68471/comment/f7ee1586_7277fd9b PS10, Line 45: 0x7B > What's the conversion of `50` -> `0x7B` (123)? Ah, 50C is 122F, so maybe this is off by 1? -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 12 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 23:01:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in qc_blobs[master]: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes f...
by Shelley Chen (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Bharath N. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/68889 ) Change subject: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can you please update the qtiseclib source to this version as well? Thanks! -- To view, visit https://review.coreboot.org/c/qc_blobs/+/68889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I3a3bf0f9c6861920e358021332af5f4f8bc7ca71 Gerrit-Change-Number: 68889 Gerrit-PatchSet: 1 Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Saurabh Gorecha <quic_sgorecha(a)quicinc.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 23:01:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in qc_blobs[master]: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes f...
by Julius Werner (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Bharath N. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/68889 ) Change subject: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69 ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/c/qc_blobs/+/68889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I3a3bf0f9c6861920e358021332af5f4f8bc7ca71 Gerrit-Change-Number: 68889 Gerrit-PatchSet: 1 Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Saurabh Gorecha <quic_sgorecha(a)quicinc.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 22:56:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
by 9elements QA (Code Review) 27 Oct '22

27 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68626 ) Change subject: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131050 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131049 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/131048 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/131047 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/131046 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131045 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/131044 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/131043 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/131042 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/131041 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/131040 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/131039 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131038 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/131037 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/131036 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/131035 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01 Gerrit-Change-Number: 68626 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ofer Fried <oferfried(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 26 Oct 2022 22:27:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/mp_init: adjust timeout for final SIPI
by Jonathan Zhang (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Arthur Heymans, Angel Pons, Felix Held. Hello Arthur Heymans, build bot (Jenkins), Marc Jones, Nico Huber, Christian Walter, Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68262 to look at the new patch set (#8). Change subject: cpu/x86/mp_init: adjust timeout for final SIPI ...................................................................... cpu/x86/mp_init: adjust timeout for final SIPI Adjust timeout for final SIPI to satisfy some to-be-launched server processors. Add a spew print to display how long it takes for the APs to be ready. This is intended to facilitate only troubleshooting and trend analysis. Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> --- M src/cpu/x86/mp_init.c 1 file changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/68262/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/68262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Gerrit-Change-Number: 68262 Gerrit-PatchSet: 8 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/x86/mp_init: adjust timeout for 2nd SIPI
by Jonathan Zhang (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Arthur Heymans, Angel Pons, Felix Held. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68262 ) Change subject: cpu/x86/mp_init: adjust timeout for 2nd SIPI ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68262/comment/de75f7a2_a3a079c9 PS7, Line 7: 2nd > i'd replace "2nd" with "final" so that this is also the correct description for the CONFIG(X86_INIT_ […] Makes sense -- To view, visit https://review.coreboot.org/c/coreboot/+/68262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Gerrit-Change-Number: 68262 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 22:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in qc_blobs[master]: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes f...
by Shelley Chen (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Julius Werner, Bharath N. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/68889 ) Change subject: sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/qc_blobs/+/68889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I3a3bf0f9c6861920e358021332af5f4f8bc7ca71 Gerrit-Change-Number: 68889 Gerrit-PatchSet: 1 Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Saurabh Gorecha <quic_sgorecha(a)quicinc.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 22:17:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
by Raul Rangel (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Jason Glenesk, EricKY Cheng, Matt DeVillier, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal ...................................................................... Patch Set 12: (1 comment) File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/fb2460c5_223be09d PS12, Line 44: TIN4 These are all device specific values. We should pull all this code into the device specific ASL code. There might need to be some refactoring to support this. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 12 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 22:15:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022