coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL
by Ivy Jian (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Tim Wawrzynczak, Nick Vaccaro. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68901 ) Change subject: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Gerrit-Change-Number: 68901 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 27 Oct 2022 00:51:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68251 ) Change subject: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS ...................................................................... soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS a) Add LTR disqualification in D3 to ensure PMC ignores LTR from UFS IP as it is infinite. b) Remove LTR disqualification in _PS0 to ensure PMC stops ignoring LTR from UFS IP during D3 exit. c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply this LTR WA. BUG=b:252975357 TEST=build and boot nirwen and see no issues in PLT runs Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/ufs.h M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi/ufs.asl 4 files changed, 58 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fe7b3a2..548ef3d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -428,6 +428,7 @@ config ALDERLAKE_ENABLE_SOC_WORKAROUND bool default y + select SOC_INTEL_UFS_LTR_DISQUALIFY select SOC_INTEL_UFS_OCP_TIMER_DISABLE help Selects the workarounds applicable for Alder Lake SoC. diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h index 3b5e33d..e3a98f2 100644 --- a/src/soc/intel/alderlake/include/soc/ufs.h +++ b/src/soc/intel/alderlake/include/soc/ufs.h @@ -22,6 +22,7 @@ #define R_SCS_PCR_5820 0x5820 #define R_SCS_PCR_5C20 0x5C20 #define R_SCS_PCR_1078 0x1078 -#define R_PMC_PWRM_LTR_IGN 0x1B0C +#define R_PMC_PWRM_LTR_IGN 0x1b0c +#define PCH_PWRM_BASE_SIZE 0x1e30 #endif diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 2b102bc..bf5fa56 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -56,4 +56,9 @@ work around the Silicon Issue due to which LTR mechanism doesn't work. +config SOC_INTEL_UFS_LTR_DISQUALIFY + bool + help + LTR needs to be disqualified for UFS in D3 to ensure PMC + ignores LTR from UFS IP which is infinite. endif diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl index f7cb9f3..a2ddaa9 100644 --- a/src/soc/intel/common/block/acpi/acpi/ufs.asl +++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/iomap.h> #include <soc/pcr_ids.h> #include <soc/ufs.h> +#define TRUE 1 +#define FALSE 0 + Scope (\_SB.PCI0) { Device (UFS) @@ -59,6 +63,18 @@ PGEN, 1 } + OperationRegion(PWMR, SystemMemory, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE) + Field(PWMR, DWordAcc, NoLock, Preserve) + { + Offset(R_PMC_PWRM_LTR_IGN), + , 18, + LTRU, 1, /* Bit 18 - Ignore LTR from UFS X2 */ + } + + Method (ULTR, 1, Serialized) { + LTRU = Arg0 + } + Method (_PS0, 0, Serialized) { /* Disable PG */ @@ -67,6 +83,11 @@ /* Set BIT[1:0] = 00b - Power State D0 */ PSTA &= 0xFFFFFFFC +#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY) + /* Remove Disqualification of LTR from UFS IP */ + ULTR (FALSE) +#endif + #if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) /* Disable OCP Timer in SCS UFS IOSF Bridge */ OCPD () @@ -75,6 +96,11 @@ Method (_PS3, 0, Serialized) { +#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY) + /* Disqualify LTR from UFS IP */ + ULTR (TRUE) +#endif + /* Enable PG */ PGEN = 1 } -- To view, visit https://review.coreboot.org/c/coreboot/+/68251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Gerrit-Change-Number: 68251 Gerrit-PatchSet: 10 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Daniil Lunev <dlunev(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/{adl, cmn}: Allow config to select the OCP workaround
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68309 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/{adl, cmn}: Allow config to select the OCP workaround ...................................................................... soc/intel/{adl, cmn}: Allow config to select the OCP workaround This patch introduces a config option for SoC code to choose the applicable SoC workaround. For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE` to apply UFS OCP timeout disable workaround. At present ADL SoC only selects so, and in future MTL and others should check with Intel prior selecting this kconfig. It's the placeholder to add more workaround in required going forward. BUG=none TEST=Able to build and boot Google/Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi/ufs.asl 3 files changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, but someone else must approve Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 92a8c06..fe7b3a2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -425,6 +425,13 @@ help Enables ACPI entry to provide silicon type information to IPU kernel driver. +config ALDERLAKE_ENABLE_SOC_WORKAROUND + bool + default y + select SOC_INTEL_UFS_OCP_TIMER_DISABLE + help + Selects the workarounds applicable for Alder Lake SoC. + choice prompt "Multiprocessor (MP) Initialization configuration to use" default USE_FSP_MP_INIT diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index e21584c..2b102bc 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -49,4 +49,11 @@ help Defines hybrid CPU specific ACPI helper functions. +config SOC_INTEL_UFS_OCP_TIMER_DISABLE + bool + help + OCP Timer need to be disabled in SCS UFS IOSF Bridge to + work around the Silicon Issue due to which LTR mechanism + doesn't work. + endif diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl index 41c14d7..f7cb9f3 100644 --- a/src/soc/intel/common/block/acpi/acpi/ufs.asl +++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl @@ -67,8 +67,10 @@ /* Set BIT[1:0] = 00b - Power State D0 */ PSTA &= 0xFFFFFFFC +#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) /* Disable OCP Timer in SCS UFS IOSF Bridge */ OCPD () +#endif } Method (_PS3, 0, Serialized) @@ -79,7 +81,9 @@ Method (_INI) { +#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) OCPD () +#endif } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Gerrit-Change-Number: 68309 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/generic/ioapic: Use register_new_ioapic_gsi0()
by Stefan Ott (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Kyösti Mälkki, Alexander Couzens, Patrick Rudolph. Stefan Ott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55315 ) Change subject: drivers/generic/ioapic: Use register_new_ioapic_gsi0() ...................................................................... Patch Set 8: Code-Review-1 (1 comment) Patchset: PS8: This doesn't compile for me (X200): CC ramstage/drivers/pc80/pc/i8254.o CC ramstage/drivers/pc80/pc/i8259.o CC ramstage/drivers/pc80/pc/isa-dma.o CC ramstage/drivers/pc80/pc/keyboard.o CC ramstage/drivers/mipi/panel.o CC ramstage/drivers/lenovo/wacom.o GCC ramstage/drivers/intel/gma/hires_fb/gma-gfx_init.o CC ramstage/drivers/intel/gma/acpi.o CC ramstage/drivers/intel/gma/edid.o GCC ramstage/drivers/intel/gma/gma.o CC ramstage/drivers/intel/gma/opregion.o CC ramstage/drivers/intel/gma/vbt.o CC ramstage/drivers/i2c/at24rf08c/at24rf08c.o CC ramstage/drivers/i2c/at24rf08c/lenovo_serials.o CC ramstage/drivers/generic/ioapic/ioapic.o src/drivers/generic/ioapic/ioapic.c: In function 'ioapic_init': src/drivers/generic/ioapic/ioapic.c:14:9: error: implicit declaration of function 'register_new_ioapic_gsi0' [-Werror=implicit-function-declaration] 14 | register_new_ioapic_gsi0(config->base); | ^~~~~~~~~~~~~~~~~~~~~~~~ src/drivers/generic/ioapic/ioapic.c: At top level: cc1: note: unrecognized command-line option '-Wno-array-compare' may have been intended to silence earlier diagnostics cc1: all warnings being treated as errors make: *** [Makefile:392: build/ramstage/drivers/generic/ioapic/ioapic.o] Error 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b03d32fa16fb9eb8a035e58bb7e3e027904f076 Gerrit-Change-Number: 55315 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Oct 2022 00:31:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: gm45 boards: Drop unneeded MP table stuff
by Stefan Ott (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Martin L Roth, Angel Pons, Arthur Heymans, Michael Niewöhner, Alexander Couzens. Stefan Ott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66611 ) Change subject: gm45 boards: Drop unneeded MP table stuff ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: Does not appear to break anything obvious on the X200. -- To view, visit https://review.coreboot.org/c/coreboot/+/66611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3feeca8a86725cb00c8035dc2cc87e28492c3fe8 Gerrit-Change-Number: 66611 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 27 Oct 2022 00:25:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Use linked list data structures
by Eric Lai (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64340 ) Change subject: cpu/x86/mp_init.c: Use linked list data structures ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie728110fc8c60fec94ae4bedf74e17740cf78f67 Gerrit-Change-Number: 64340 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Oct 2022 00:12:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL
by Eric Lai (Code Review) 27 Oct '22

27 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Tim Wawrzynczak, Nick Vaccaro, Ivy Jian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68901 ) Change subject: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Gerrit-Change-Number: 68901 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Oct 2022 00:10:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: 3rdparty/amd_blobs:Advance submodule pointer
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68870 ) Change subject: 3rdparty/amd_blobs:Advance submodule pointer ...................................................................... 3rdparty/amd_blobs:Advance submodule pointer This picks up the following changes: 4ed38e55 glinda: add placeholder blobs 6de2d3c2 mendocino: Add all blobs from PI 1.0.0.3 Change-Id: Ic2d024f9e5dcd73abed9123b6a6255fe0c28fd4a Signed-off-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68870 Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/amd_blobs 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 234dc70..4ed38e5 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 234dc706701b8c02f8c70dd3089544c0097a09bd +Subproject commit 4ed38e55a098024166f8cdbef24239bce453c2e5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d024f9e5dcd73abed9123b6a6255fe0c28fd4a Gerrit-Change-Number: 68870 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/amdfwtool/amdfwread: Update relative_offset function
by 9elements QA (Code Review) 27 Oct '22

27 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66572 ) Change subject: util/amdfwtool/amdfwread: Update relative_offset function ...................................................................... Patch Set 16: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 2 / 15 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131068 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131067 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/131066 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/131065 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/131064 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131063 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/131062 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/131061 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/131060 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/131058 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/131057 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131056 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/131055 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/131054 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/131053 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/66572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126 Gerrit-Change-Number: 66572 Gerrit-PatchSet: 16 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 23:58:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generation
by Felix Held (Code Review) 27 Oct '22

27 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68850 ) Change subject: mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generation ...................................................................... mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generation This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Guybrush, Skyrim and Zork. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68850 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/zork/mainboard.c 3 files changed, 78 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 150835c..8deb2ac 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -74,18 +74,32 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + static void init_tables(void) { - const struct fch_irq_routing *entry; - int i; + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - for (i = 0; i < ARRAY_SIZE(fch_irq_map); i++) { - entry = fch_irq_map + i; - fch_pic_routing[entry->intr_index] = entry->pic_irq_num; - fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; } } diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 0469c59..ca3c9aa 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -60,18 +60,32 @@ { PIRQ_HPET_H, 0x00, 0x00 }, }; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + static void init_tables(void) { - const struct fch_irq_routing *entry; - int i; + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - for (i = 0; i < ARRAY_SIZE(fch_irq_map); i++) { - entry = fch_irq_map + i; - fch_pic_routing[entry->intr_index] = entry->pic_irq_num; - fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; } } diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index a925851..aaa2548 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -78,18 +78,32 @@ { PIRQ_MISC2, 0x00, 0x00 }, }; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + static void init_tables(void) { - const struct fch_irq_routing *entry; - int i; + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); - for (i = 0; i < ARRAY_SIZE(fch_irq_map); i++) { - entry = fch_irq_map + i; - fch_pic_routing[entry->intr_index] = entry->pic_irq_num; - fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6 Gerrit-Change-Number: 68850 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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