coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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5881 discussions

[S] Change in coreboot[master]: mb/google/brya : Update EPP value for Vell board
by Gaggery Tsai (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Kedar J. Karanje, Tim Wawrzynczak, Sridhar Siricilla, Kane Chen. Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68900 ) Change subject: mb/google/brya : Update EPP value for Vell board ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: register "enable_energy_perf_pref" = "true" is required to make it work. -- To view, visit https://review.coreboot.org/c/coreboot/+/68900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae Gerrit-Change-Number: 68900 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 21:03:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: coreboot_tables: Drop uart PCI addr
by 9elements QA (Code Review) 26 Oct '22

26 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68767 ) Change subject: coreboot_tables: Drop uart PCI addr ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131033 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131032 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/131031 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/131030 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/131029 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131028 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/131027 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/131026 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/131025 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/131024 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/131023 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/131022 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131021 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/131020 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/131019 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/131018 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Gerrit-Change-Number: 68767 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 20:55:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT
by Paul Menzel (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Jon Murphy, Nelson Ye, Martin Roth, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68742 ) Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68742/comment/91186164_e97794a3 PS1, Line 9: thermal table config E > Hi Paul, […] Please add that summary to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/68742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Gerrit-Change-Number: 68742 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Isaac Lee <isaaclee(a)google.com> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 20:39:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts
by Tim Van Patten (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Nien, EricKY Cheng, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68642 ) Change subject: mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa6169c6e824318e738878f8cd19e76fcfd5713 Gerrit-Change-Number: 68642 Gerrit-PatchSet: 2 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 20:16:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts
by Karthik Ramasubramanian (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Nien, EricKY Cheng, Martin Roth, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68642 ) Change subject: mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa6169c6e824318e738878f8cd19e76fcfd5713 Gerrit-Change-Number: 68642 Gerrit-PatchSet: 2 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 19:35:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Disable S3
by 9elements QA (Code Review) 26 Oct '22

26 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68591 ) Change subject: mb/prodrive/atlas: Disable S3 ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131016 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/131015 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/131014 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/131013 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/131012 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131011 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/131010 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/131009 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/131008 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/131007 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/131006 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/131005 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/131004 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/131003 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/131002 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/131001 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Gerrit-Change-Number: 68591 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 19:24:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/LinuxBoot: Fix Linuxboot kernel fetching for v6.x
by 9elements QA (Code Review) 26 Oct '22

26 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68815 ) Change subject: payloads/LinuxBoot: Fix Linuxboot kernel fetching for v6.x ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130999 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130998 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130997 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130996 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130995 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130994 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130993 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130992 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130991 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130990 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130989 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130988 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130987 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130986 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130985 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130984 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d407eab8ec4569e02729afb5c71f39ce174401 Gerrit-Change-Number: 68815 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 18:31:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: spd/lp5: Re-generate the SPD data
by Karthik Ramasubramanian (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: EricKY Cheng, Chris Wang. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68873 ) Change subject: spd/lp5: Re-generate the SPD data ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19ae0477dea64f2cdd37b6aa51eadd6957c54059 Gerrit-Change-Number: 68873 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 18:28:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Update Crota's ELAN touchscreen delay to 150 ms
by Subrata Banik (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Paz Zcharya, Terry Chen, Tim Wawrzynczak, Nick Vaccaro, Franklin Lin, Rajat Jain. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68868 ) Change subject: mb/google/brya: Update Crota's ELAN touchscreen delay to 150 ms ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/variants/crota/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68868/comment/8b76812b_d442fcbb PS6, Line 225: 150 > This delay is "parallelized" with other initializatoin operations, and since they are in seconds, this delay does not matter. (Even if we had 0 delay, ther delays in other drivers take care of it at boot time). But then we introduce this unstated dependency on other drivers taking > x ms. That is problem 1. > > Other problem is that at resume time, things go a lot faster (our resume time expectation is within 500ms). There also we parallelize this delay, but we'd like to have a way to ensure what is the minimum delay before which the touschscreen can become funtional. lets continue this discussion over a bug? -- To view, visit https://review.coreboot.org/c/coreboot/+/68868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17e1f7d419637f6dff4049484ce1836ad98017ea Gerrit-Change-Number: 68868 Gerrit-PatchSet: 6 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Franklin Lin <franklin_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rajat Jain <rajatja(a)google.com> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Franklin Lin <franklin_lin(a)wistron.corp-partner.google.com> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 18:07:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paz Zcharya <pazz(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES
by Felix Held (Code Review) 26 Oct '22

26 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68818 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES ...................................................................... soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/birman/mainboard.c M src/mainboard/amd/chausie/mainboard.c M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/majolica/mainboard.c M src/mainboard/amd/mandolin/mainboard.c M src/mainboard/amd/pademelon/mainboard.c M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/zork/mainboard.c M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h 12 files changed, 45 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index c402c29..324c72e 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -27,11 +27,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; static const struct fch_irq_routing bilby_fch[] = { { PIRQ_A, 8, 16 }, diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c index 34c3b4d..8b27e37 100644 --- a/src/mainboard/amd/birman/mainboard.c +++ b/src/mainboard/amd/birman/mainboard.c @@ -18,11 +18,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; /* * This controls the device -> IRQ routing. diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c index 9251ff2..0318e43 100644 --- a/src/mainboard/amd/chausie/mainboard.c +++ b/src/mainboard/amd/chausie/mainboard.c @@ -16,11 +16,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; /* * This controls the device -> IRQ routing. diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index b9c2eaf..8a4da9f 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -19,7 +19,7 @@ * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. */ -static const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, @@ -38,7 +38,7 @@ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, }; -static const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = { [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index 58f7546..32b29e4 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -15,11 +15,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; /* * This controls the device -> IRQ routing. diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 0f87d9c..6ae3266 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -22,11 +22,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; static const struct fch_irq_routing mandolin_fch[] = { { PIRQ_A, 8, 16 }, diff --git a/src/mainboard/amd/pademelon/mainboard.c b/src/mainboard/amd/pademelon/mainboard.c index a013e6c..2e55009 100644 --- a/src/mainboard/amd/pademelon/mainboard.c +++ b/src/mainboard/amd/pademelon/mainboard.c @@ -20,7 +20,7 @@ * These values are used by the PCI configuration space, * MP Tables. */ -static const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, @@ -39,7 +39,7 @@ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, }; -static const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = { [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 4bcb52e..bfb0f88 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -30,11 +30,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; /* * This controls the device -> IRQ routing. diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 2cd88b8..196d6b8 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -30,7 +30,7 @@ * MP Tables. TODO: Make ACPI use these values too. */ -static const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, @@ -49,7 +49,7 @@ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, }; -static const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = { [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17, [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 0b707d7..58e11f5 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -16,11 +16,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; /* * This controls the device -> IRQ routing. diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index fedf1cc..bab79b4 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -39,11 +39,8 @@ * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. */ -static uint8_t fch_pic_routing[0x80]; -static uint8_t fch_apic_routing[0x80]; - -_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), - "PIC and APIC FCH interrupt tables must be the same size"); +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; /* * This controls the device -> IRQ routing. diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 6543853..c766d50 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -11,6 +11,8 @@ #define PCI_INTR_INDEX 0xc00 #define PCI_INTR_DATA 0xc01 +#define FCH_IRQ_ROUTING_ENTRIES 0x80 + struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; -- To view, visit https://review.coreboot.org/c/coreboot/+/68818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Gerrit-Change-Number: 68818 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2022