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Change subject: mb/google/rex: Add fingerprint SPI
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/google/rex/variants/rex0/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161606):
https://review.coreboot.org/c/coreboot/+/66992/comment/adda9e78_e0ca269c
PS13, Line 443: /* GPP_C23 : [] ==> FP_RST_ODL */
code indent should use tabs where possible
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/66992
to look at the new patch set (#13).
Change subject: mb/google/rex: Add fingerprint SPI
......................................................................
mb/google/rex: Add fingerprint SPI
Add Fingerprint SPI, and power-off FPMCU during romstage.
for reference see CL:66915 for a similar change to Brya's power sequence
TEST=None yet. Awaiting Hardware
Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/rex0/gpio.c
M src/mainboard/google/rex/variants/rex0/overridetree.cb
3 files changed, 40 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/66992/13
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Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68927 )
Change subject: soc/amd/common: Initialize STB Spill-to-DRAM
......................................................................
Patch Set 1: Code-Review+2
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Change subject: commonlib...cbmem_id.h: Add AMD STB buffer IDs for CBMEM
......................................................................
Patch Set 1:
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h:
https://review.coreboot.org/c/coreboot/+/68926/comment/5a739faa_0a2354b2
PS1, Line 164: { CBMEM_ID_AMD_STB, "AMD MP2 BUFFER"}
> nit: Should this have a blank line before the #endif? […]
We still need to add a backslash at the end when adding another entry.
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68546 )
Change subject: soc/amd/common: Add coreboot post codes to STB
......................................................................
soc/amd/common: Add coreboot post codes to STB
Adding coreboot's postcodes to the smart trace buffer lets us see the
entire boot flow in one place.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/common/block/include/amdblocks/stb.h
M src/soc/amd/common/block/stb/Kconfig
M src/soc/amd/common/block/stb/stb.c
3 files changed, 29 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Fred Reitberger: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/stb.h b/src/soc/amd/common/block/include/amdblocks/stb.h
index 51b0194..c8851f8 100644
--- a/src/soc/amd/common/block/include/amdblocks/stb.h
+++ b/src/soc/amd/common/block/include/amdblocks/stb.h
@@ -7,6 +7,7 @@
#define AMD_STB_PMI_0 0x30600
+#define AMD_STB_COREBOOT_POST_PREFIX 0xBA000000
#define AMD_STB_COREBOOT_MARKER 0xBAADF00D
struct stb_entry_struct {
diff --git a/src/soc/amd/common/block/stb/Kconfig b/src/soc/amd/common/block/stb/Kconfig
index 8935e92..fe2b5b7 100644
--- a/src/soc/amd/common/block/stb/Kconfig
+++ b/src/soc/amd/common/block/stb/Kconfig
@@ -14,4 +14,10 @@
points through the boot process. Note that this will prevent the
entries from being stored if the Spill-to-DRAM feature is enabled.
+config ADD_POSTCODES_TO_STB
+ bool "Add coreboot postcodes to STB"
+ default y
+ help
+ Add coreboot's postcodes to the smart trace buffer
+
endif
diff --git a/src/soc/amd/common/block/stb/stb.c b/src/soc/amd/common/block/stb/stb.c
index 074a4ed..0cea5c3 100644
--- a/src/soc/amd/common/block/stb/stb.c
+++ b/src/soc/amd/common/block/stb/stb.c
@@ -18,6 +18,12 @@
return smn_read32(STB_CFG_SMN_ADDR + reg);
}
+void soc_post_code(uint8_t value)
+{
+ if (CONFIG(ADD_POSTCODES_TO_STB))
+ stb_write32(AMD_STB_PMI_0, AMD_STB_COREBOOT_POST_PREFIX | value);
+}
+
void write_stb_to_console(void)
{
int i;
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68543 )
Change subject: soc/amd/common: Add code to print AMD STB to boot log
......................................................................
soc/amd/common: Add code to print AMD STB to boot log
This allows platforms that support AMD's STB (Smart Trace Buffer) to
print the buffer at various points in the boot process.
The STB is roughly a hardware assisted postcode that captures the
time stamp of when the postcode was added to the buffer. Reading
from the STB clears the data.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I8d78c0e86b244f3bd16248edf3850447fb0a9e2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68543
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---
A src/soc/amd/common/block/include/amdblocks/stb.h
A src/soc/amd/common/block/stb/Kconfig
A src/soc/amd/common/block/stb/Makefile.inc
A src/soc/amd/common/block/stb/stb.c
4 files changed, 132 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Fred Reitberger: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/stb.h b/src/soc/amd/common/block/include/amdblocks/stb.h
new file mode 100644
index 0000000..51b0194
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/stb.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_STB_H
+#define AMD_BLOCK_STB_H
+
+#include <types.h>
+
+#define AMD_STB_PMI_0 0x30600
+
+#define AMD_STB_COREBOOT_MARKER 0xBAADF00D
+
+struct stb_entry_struct {
+ uint32_t ts;
+ uint32_t val;
+};
+
+void write_stb_to_console(void);
+void init_spill_buffer(void);
+void add_stb_to_timestamp_buffer(void);
+
+#endif /* AMD_BLOCK_STB_H */
diff --git a/src/soc/amd/common/block/stb/Kconfig b/src/soc/amd/common/block/stb/Kconfig
new file mode 100644
index 0000000..8935e92
--- /dev/null
+++ b/src/soc/amd/common/block/stb/Kconfig
@@ -0,0 +1,17 @@
+config SOC_AMD_COMMON_BLOCK_STB
+ bool
+ select SOC_AMD_COMMON_BLOCK_SMN
+ help
+ Select in the SOC if it supports the Smart Trace Buffer
+
+if SOC_AMD_COMMON_BLOCK_STB
+
+config WRITE_STB_BUFFER_TO_CONSOLE
+ bool "Write STB entries to the console log"
+ default n
+ help
+ This option will tell coreboot to print the STB buffer at various
+ points through the boot process. Note that this will prevent the
+ entries from being stored if the Spill-to-DRAM feature is enabled.
+
+endif
diff --git a/src/soc/amd/common/block/stb/Makefile.inc b/src/soc/amd/common/block/stb/Makefile.inc
new file mode 100644
index 0000000..5ce9c4b
--- /dev/null
+++ b/src/soc/amd/common/block/stb/Makefile.inc
@@ -0,0 +1,7 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_STB),y)
+
+bootblock-y += stb.c
+romstage-y += stb.c
+ramstage-y += stb.c
+
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_STB
diff --git a/src/soc/amd/common/block/stb/stb.c b/src/soc/amd/common/block/stb/stb.c
new file mode 100644
index 0000000..074a4ed
--- /dev/null
+++ b/src/soc/amd/common/block/stb/stb.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/smn.h>
+#include <amdblocks/stb.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <soc/stb.h>
+
+#define STB_ENTRIES_PER_ROW 4
+
+static void stb_write32(uint32_t reg, uint32_t val)
+{
+ smn_write32(STB_CFG_SMN_ADDR + reg, val);
+}
+
+static uint32_t stb_read32(uint32_t reg)
+{
+ return smn_read32(STB_CFG_SMN_ADDR + reg);
+}
+
+void write_stb_to_console(void)
+{
+ int i;
+ int printed_data = 0;
+ struct stb_entry_struct stb_val;
+
+ /* Add a marker into the STB so it's easy to see where the end is. */
+ stb_write32(AMD_STB_PMI_0, AMD_STB_COREBOOT_MARKER);
+
+ for (i = 0; i < AMD_STB_SDRAM_FIFO_SIZE; i++) {
+ /*
+ * It's possible to do a single read and leave the timestamp as the first
+ * value of a pair, but by default the value will be first and time stamp
+ * second. We're just assuming that nothing has messed up the ordering.
+ */
+ stb_val.val = stb_read32(AMD_STB_PMI_0);
+ stb_val.ts = stb_read32(AMD_STB_PMI_0);
+
+ if (stb_val.val == AMD_STB_COREBOOT_MARKER) {
+ if (!printed_data)
+ printk(BIOS_DEBUG, "No Smart Trace Buffer Data available.\n");
+ else
+ // Don't print the coreboot marker
+ printk(BIOS_DEBUG, "\n");
+ return;
+ }
+
+ if (i == 0)
+ printk(BIOS_DEBUG, "Available Smart Trace Buffer data:\n");
+ if ((i % STB_ENTRIES_PER_ROW) == 0)
+ printk(BIOS_DEBUG, "%04d,", i);
+ printk(BIOS_DEBUG, " 0x%08x,0x%08x, ", stb_val.ts, stb_val.val);
+ if ((i % STB_ENTRIES_PER_ROW) == STB_ENTRIES_PER_ROW - 1)
+ printk(BIOS_DEBUG, "\n");
+ printed_data = 1;
+
+ }
+
+}
+
+static void final_stb_console(void *unused)
+{
+ if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE))
+ write_stb_to_console();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, final_stb_console, NULL);
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Change subject: stoneyridge: Set the SPI read speed as 66MHz
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> wait for more test.
Please mark it as WIP then.
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Change subject: mb/google/skyrim: Implement touchscreen power sequencing
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/67778/comment/2292bb97_d3b2088d
PS3, Line 116: /* EN_PP3300_TCHSCR */
: PAD_GPO(GPIO_131, LOW),
: /* TCHSCR_RESET_L */
: PAD_GPO(GPIO_136, LOW),
> I agree with Karthik that we should add the FW_CONFIG bit for all future devices. […]
Filed b/255965286 to look at adding FW_CFG.
In the meantime, I think we're good here.
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