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Change subject: soc/amd/common: Initialize STB Spill-to-DRAM
......................................................................
Patch Set 1: Code-Review+2
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Change subject: allocator_v4: Use memranges only for toplevel
......................................................................
Patch Set 9:
(1 comment)
File src/device/resource_allocator_v4.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161593):
https://review.coreboot.org/c/coreboot/+/65420/comment/ad5587e3_3ef5bef5
PS9, Line 561: void assign_resource_cb(void *param, struct device *dev, struct resource *res)
open brace '{' following function definitions go on the next line
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Jonathan Zhang has uploaded a new patch set (#9) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/65420 )
Change subject: allocator_v4: Use memranges only for toplevel
......................................................................
allocator_v4: Use memranges only for toplevel
During phase 1 of the resource allocation we gather all the size
requirements. Starting from the leafs of our devicetree, we cal-
culate the requirements per bus, until we reach the resource do-
main.
However, because alignment plays a role, we can't just accumulate
the sizes of all resources on a bus. Instead, we already sort all
the resources per bus to predict their relative placement, inclu-
ding alignment gaps. Then, phase 2 has to perform the final allo-
cations with the exact same relative placement.
This patch introduces a very simple mechanism to avoid repeating
all the calculations: In phase 1, we note the relative `base` of
each resource on a bus. And after we allocated all the resources
directly below the domain in phase 2, we add the absolute `base`
of bridge resources to the relative `base` of child resources.
This saves most of the computational complexity in phase 2. How-
ever, with a shallow devicetree with most devices directly below
the domain, this won't have a measurable impact.
Example after phase 1:
domain
|
`-- bridge #0
| res #0, base 0x000000 (relative),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
After phase 2 allocation at the domain level (assuming res #0 got
0xa000000 assigned):
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
Now, all we need to do is to add the `base` of bridge resources
recursively. Starting with resources on the bus below bridge #0:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
And finally for resources on the bus below bridge #1:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0xa000000 (absolute),
size 8M, align 8M
Change-Id: I70c700318a85f6760f27597730bc9c9a86dbe6b3
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/resource_allocator_v4.c
1 file changed, 257 insertions(+), 144 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/65420/9
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Change subject: commonlib...cbmem_id.h: Add AMD STB buffer IDs for CBMEM
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h:
https://review.coreboot.org/c/coreboot/+/68926/comment/b929013e_2c6de610
PS1, Line 164: { CBMEM_ID_AMD_STB, "AMD MP2 BUFFER"}
nit: Should this have a blank line before the #endif?
nit: Would it break anything if there is a comma at the end of this line? That way fewer lines would change in the future when more IDs are added.
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Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68706
to look at the new patch set (#2).
Change subject: MAINTAINERS: Add orphaned mainboards
......................................................................
MAINTAINERS: Add orphaned mainboards
The mainboards are broken out into individual entries in hopes that it
will be easier for someone to claim ownership than if they were lumped
into a single "Orphaned Mainboards" group.
The theory behind this is that a single mainboard is really the easiest
piece of coreboot to maintain. Hopefully some less-experienced people
will be interested in stepping up to take over ownership of a mainboard.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I9542b3a7cd87fa8656bc0982c08061e9d0513745
---
M MAINTAINERS
1 file changed, 186 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/68706/2
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68706 )
Change subject: MAINTAINERS: Add orphaned mainboards
......................................................................
Patch Set 1:
(3 comments)
Patchset:
PS1:
> Our (Angel's) thoughts on this: as maintainers for various Intel CPUs/chipsets, we maintain the main […]
I get what you're saying, but I don't think you maintain the mainboard in the same way. It's more about updating to match changes in chipset code than specifically adding new mainboard features.
I'd also think that mainboard maintainers would generally be able to test the mainboard. Otherwise, it's very difficult to maintain.
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/68706/comment/33778319_f22a5b32
PS1, Line 266: COMPULAB MAINBOARDS
> nit: Add empty line above it
Done
https://review.coreboot.org/c/coreboot/+/68706/comment/52036d35_6e724996
PS1, Line 430: JETWAY MAINBOARDS
> nit: Add an empty line above it
Done
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Change subject: soc/amd/common: Add coreboot post codes to STB
......................................................................
Patch Set 4: Code-Review+2
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Change subject: ec/google/chromec: Add DPTC support for host event 1/2/9
......................................................................
Patch Set 13: Code-Review+1
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 16 DPTC thermal parameters
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68649/comment/20f23488_9abe4688
PS9, Line 7: 16
nit: 13
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/3632ca1d_20299422
PS9, Line 264: /* Profile B */
> I will submit a new CL for new config.
Unresolving until this is blocked by the new config value.
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