coreboot-gerrit January 2022

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Change in coreboot[master]: mb/google/brya/var/brask: Change TPM I2C to I2C1
by Tim Wawrzynczak (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: David Wu, Paul Menzel, Nick Vaccaro, Alan Huang, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60439 ) Change subject: mb/google/brya/var/brask: Change TPM I2C to I2C1 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c Gerrit-Change-Number: 60439 Gerrit-PatchSet: 4 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:18:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Change TPM I2C to I2C1
by Tim Wawrzynczak (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: David Wu, Paul Menzel, Nick Vaccaro, Alan Huang, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60439 ) Change subject: mb/google/brya/var/brask: Change TPM I2C to I2C1 ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60439/comment/8570ef2e_b002a336 PS4, Line 9: latest schematics > Boards with older schematics were not sold, right? No, brask is very much still in development. File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60439/comment/0dddf523_d85cd0d4 PS4, Line 91: .rise_time_ns = 600, : .fall_time_ns = 400, : .data_hold_time_ns = 50, > Where are these values from? I imagine these were borrowed from brya? -- To view, visit https://review.coreboot.org/c/coreboot/+/60439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c Gerrit-Change-Number: 60439 Gerrit-PatchSet: 4 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:18:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
by Tim Wawrzynczak (Code Review) 04 Jan '22

04 Jan '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60341 ) Change subject: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC ...................................................................... mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC Taeko will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:211914322 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend: chromium:3358662 Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 12 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 7900172..44b9503 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -241,6 +241,7 @@ .clk_req = 0, .clk_src = 0, }" + probe BOOT_NVME_MASK BOOT_NVME_ENABLED end device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end @@ -396,12 +397,21 @@ end end device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" - register "srcclk_pin" = "1" - device generic 0 on end + register "srcclk_pin" = "0" + device generic 0 on + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED + end end + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end device ref gspi1 on chip drivers/spi/acpi 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573 Gerrit-Change-Number: 60341 Gerrit-PatchSet: 15 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/sarien/var/sarien: Add VBT from Chromebook firmware
by Tim Wawrzynczak (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Felix Singer, Matt DeVillier, Paul Menzel, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60735 ) Change subject: mb/google/sarien/var/sarien: Add VBT from Chromebook firmware ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > Where are the VBTs in the Chromium repositories? […] Just FYI, we have some work planned to make Chrome OS firmware buildable from public repos, at least after they're released. I don't have any ETAs yet, but we are planning on it. -- To view, visit https://review.coreboot.org/c/coreboot/+/60735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Gerrit-Change-Number: 60735 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:15:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add config to disable CSE at pre-boot
by Subrata Banik (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60721 ) Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/60721/comment/a134a48e_31b29675 PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot. > DISABLE_HECI1 sounds good. Sure. > > NB. If 16.0 is hidden but any of the others is not, that would violate > PCI anyway (a multi-function device must have a function 0). Effectively, > it would hide all functions from enumeration (they can still be accessed > individually when you know that they are there). Agree. -- To view, visit https://review.coreboot.org/c/coreboot/+/60721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Gerrit-Change-Number: 60721 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Add new memory support
by 9elements QA (Code Review) 04 Jan '22

04 Jan '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60410 ) Change subject: mb/google/brya/var/redrix: Add new memory support ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/87596 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/87595 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87594 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/87593 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/87592 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/87591 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87590 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/87589 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/87588 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/87587 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/60410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32491f86813c8e6566774d4b3d7d82295f906bd3 Gerrit-Change-Number: 60410 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:02:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/sarien/var/sarien: Add VBT from Chromebook firmware
by Matt DeVillier (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Felix Singer, Paul Menzel, Tim Wawrzynczak, Angel Pons. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60735 ) Change subject: mb/google/sarien/var/sarien: Add VBT from Chromebook firmware ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Is it the same? If not, where could I get it? I just dumped the recovery image and there are separate firmware images for Sarien and Arcada, but both use the same VBT -- so just need to move it to the mainboard root and add an entry in Kconfig as so: config INTEL_GMA_VBT_FILE default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" -- To view, visit https://review.coreboot.org/c/coreboot/+/60735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Gerrit-Change-Number: 60735 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:01:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add config to disable CSE at pre-boot
by Nico Huber (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60721 ) Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/60721/comment/3ab4daa5_39beb3af PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot. > > Hmm, Why not keep HECI in the name? DISABLE_HECI or HIDE_HECI […] DISABLE_HECI1 sounds good. NB. If 16.0 is hidden but any of the others is not, that would violate PCI anyway (a multi-function device must have a function 0). Effectively, it would hide all functions from enumeration (they can still be accessed individually when you know that they are there). -- To view, visit https://review.coreboot.org/c/coreboot/+/60721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Gerrit-Change-Number: 60721 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 15:55:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Check clkreq overlap
by Subrata Banik (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60401 ) Change subject: soc/intel/alderlake: Check clkreq overlap ...................................................................... Patch Set 5: -Code-Review (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60401/comment/4bd8e754_3aba5f7f PS5, Line 51: static > Hold on, we don't want this to be a static variable, otherwise it will keep its value between the tw […] ahh, yes. valid point. why we need this variable to be static. its just a bit wise for RPs. -- To view, visit https://review.coreboot.org/c/coreboot/+/60401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344 Gerrit-Change-Number: 60401 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 15:40:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Disable autonomous GPIO power management
by Tim Wawrzynczak (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: David Wu, Paul Menzel, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60388 ) Change subject: mb/google/brya/var/kano: Disable autonomous GPIO power management ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60388/comment/08ddfa8d_13bd4e53 PS3, Line 11: > Is the cr50 FW being fixed, so this is just a workaround? For existing cr50 stock, this is the FW version that comes straight out of the factory, so the first boot has to be able to deal with this version. -- To view, visit https://review.coreboot.org/c/coreboot/+/60388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9607af42a00c1b5f38c6e4e0effdeeaba18af5ff Gerrit-Change-Number: 60388 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 15:40:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit January 2022