coreboot-gerrit January 2022

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Change in coreboot[master]: mb/google/sarien: Add VBT extracted from Chrome OS
by Paul Menzel (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Felix Singer, Matt DeVillier, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60735 ) Change subject: mb/google/sarien: Add VBT extracted from Chrome OS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > Is it the same? If not, where could I get it? […] Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/60735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Gerrit-Change-Number: 60735 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 17:16:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/sarien/Kconfig: Remove blank line at beginning
by Paul Menzel (Code Review) 04 Jan '22

04 Jan '22

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60767 ) Change subject: mb/google/sarien/Kconfig: Remove blank line at beginning ...................................................................... mb/google/sarien/Kconfig: Remove blank line at beginning Change-Id: I0410be48f360bdd00e4ed7599cbee405915344b9 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/google/sarien/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/60767/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 11f7ac0..42c3aba 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -1,4 +1,3 @@ - config BOARD_GOOGLE_BASEBOARD_SARIEN def_bool n select BOARD_ROMSIZE_KB_32768 -- To view, visit https://review.coreboot.org/c/coreboot/+/60767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0410be48f360bdd00e4ed7599cbee405915344b9 Gerrit-Change-Number: 60767 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/sarien: Add VBT extracted from Chrome OS
by Paul Menzel (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Felix Singer, Matt DeVillier, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Matt DeVillier, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60735 to look at the new patch set (#2). Change subject: mb/google/sarien: Add VBT extracted from Chrome OS ...................................................................... mb/google/sarien: Add VBT extracted from Chrome OS The VBT is extracted from Chromium OS in developer mode with the device running firwmare . $ sudo dmesg | grep ' DMI:' [ 0.000000] DMI: Dell Inc. Sarien/Sarien, BIOS Google_Sarien.12200.99.0 07/29/2020 $ sudo cbmem -1 coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 bootblock starting (log level: 8)... […] coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 ramstage starting (log level: 8)... […] CBFS: Locating 'vbt.bin' CBFS: Found @ offset 614c0 size 4a0 Found a VBT of 4608 bytes after decompression […] $ sudo cp /sys/kernel/debug/dri/0/i915_vbt vbt.bin Using the Chrome OS recovery image, Matt DeVillier verified, that the Sarien VBT is identical to Arcada, so add the VBT for all variants. Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/google/sarien/Kconfig A src/mainboard/google/sarien/data.vbt 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/60735/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Gerrit-Change-Number: 60735 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/drivers: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60552 ) Change subject: src/drivers: Remove unused <string.h> ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60552/comment/38b90c56_d6815400 PS6, Line 10: snprintf hum, something went to wrong ? -- To view, visit https://review.coreboot.org/c/coreboot/+/60552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6c5b67af1d2544159e92d4b8c06cc1f5504bd2 Gerrit-Change-Number: 60552 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 17:14:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/superio/smsc: Remove unused <stdlib.h>
by HAOUAS Elyes (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Felix Held. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60616 ) Change subject: src/superio/smsc: Remove unused <stdlib.h> ...................................................................... Patch Set 3: (1 comment) File src/superio/smsc/sch5545/superio.c: https://review.coreboot.org/c/coreboot/+/60616/comment/c68e10d3_c0f99f35 PS3, Line 9: #include <stdlib.h> > indeed , <types.h> is missing. […] maybe just <stdint.h> noticed also that <commonlib/bsd/helpers.h> is missing for "ARRAY_SIZE" -- To view, visit https://review.coreboot.org/c/coreboot/+/60616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb747bcb702a81750a927272432666ffe603ca55 Gerrit-Change-Number: 60616 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Jan 2022 17:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src/superio/smsc: Remove unused <stdlib.h>
by HAOUAS Elyes (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Felix Held. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60616 ) Change subject: src/superio/smsc: Remove unused <stdlib.h> ...................................................................... Patch Set 3: (1 comment) File src/superio/smsc/sch5545/superio.c: https://review.coreboot.org/c/coreboot/+/60616/comment/bc98f58d_ff2a11e8 PS3, Line 9: #include <stdlib.h> > i wonder if that was meant to be stdint. […] indeed , <types.h> is missing. maybe we can fix in a separate patch -- To view, visit https://review.coreboot.org/c/coreboot/+/60616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb747bcb702a81750a927272432666ffe603ca55 Gerrit-Change-Number: 60616 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Jan 2022 17:02:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Set vGPIO reset type
by 9elements QA (Code Review) 04 Jan '22

04 Jan '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60334 ) Change subject: mb/google/brya/var/kano: Set vGPIO reset type ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 2 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/87618 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/87617 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87616 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/87615 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/87614 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/87613 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87612 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/87611 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/87610 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/87609 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/60334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b Gerrit-Change-Number: 60334 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:39:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add config to disable CSE at pre-boot
by Felix Singer (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Nico Huber, Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60721 ) Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/60721/comment/de245c97_1113ae64 PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot. > > DISABLE_HECI1 sounds good. […] I also wouldn't use "CSE" in the name, since for me CSE refers to the firmware, some internals of it or the hardware part and this is just about the communication interface. However, I would just use HECI1. Also, I wouldn't invert the option. I think we should be more consistent regarding the direction (enable or disable) of options. If find it pretty hard and also annoying to use the Kconfig menu if some have "enable" and others "disable" in their name. From my perspective, people expect the "enable" terminology in user interfaces. So I would name it "Enable HECI1" and set it to enable by default. -- To view, visit https://review.coreboot.org/c/coreboot/+/60721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Gerrit-Change-Number: 60721 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 16:35:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create volmar variant
by David Wu (Code Review) 04 Jan '22

04 Jan '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60766 ) Change subject: mb/google/brya: Create volmar variant ...................................................................... mb/google/brya: Create volmar variant Create the volmar variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:213127419 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VOLMAR Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I5ebf62b7a17b075c0e28fb4e8b7c501fc8db3ea3 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/volmar/include/variant/ec.h A src/mainboard/google/brya/variants/volmar/include/variant/gpio.h A src/mainboard/google/brya/variants/volmar/memory/Makefile.inc A src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/volmar/overridetree.cb 8 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/60766/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5169324..c9b335a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -104,6 +104,7 @@ default 0x3 if BOARD_GOOGLE_TANIKS default 0x0 if BOARD_GOOGLE_NIVVIKS default 0x0 if BOARD_GOOGLE_NEREID + default 0x1 if BOARD_GOOGLE_VOLMAR config DRIVER_TPM_I2C_ADDR hex @@ -145,6 +146,7 @@ default "Taniks" if BOARD_GOOGLE_TANIKS default "Nivviks" if BOARD_GOOGLE_NIVVIKS default "Nereid" if BOARD_GOOGLE_NEREID + default "Volmar" if BOARD_GOOGLE_VOLMAR config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -166,6 +168,7 @@ default "taniks" if BOARD_GOOGLE_TANIKS default "nivviks" if BOARD_GOOGLE_NIVVIKS default "nereid" if BOARD_GOOGLE_NEREID + default "volmar" if BOARD_GOOGLE_VOLMAR config VBOOT select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index e2a4a9e..739d6a5 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -143,3 +143,7 @@ config BOARD_GOOGLE_NEREID bool "-> Nereid" select BOARD_GOOGLE_BASEBOARD_NISSA + +config BOARD_GOOGLE_VOLMAR + bool "-> Volmar" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/volmar/include/variant/ec.h b/src/mainboard/google/brya/variants/volmar/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/volmar/include/variant/gpio.h b/src/mainboard/google/brya/variants/volmar/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc b/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/60766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ebf62b7a17b075c0e28fb4e8b7c501fc8db3ea3 Gerrit-Change-Number: 60766 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid
by Tim Wawrzynczak (Code Review) 04 Jan '22

04 Jan '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60271 ) Change subject: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid ...................................................................... mb/google/brya: Add new baseboard nissa with variants nivviks and nereid Add a new baseboard for nissa, an Intel ADL-N based reference design. Also, add variants for the two reference boards, nivviks and nereid. This commit is a stub which only adds the minimum code needed for a successful build. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5 Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60271 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc A src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb A src/mainboard/google/brya/variants/baseboard/nissa/gpio.c A src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h A src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h A src/mainboard/google/brya/variants/baseboard/nissa/memory.c A src/mainboard/google/brya/variants/nereid/include/variant/ec.h A src/mainboard/google/brya/variants/nereid/include/variant/gpio.h A src/mainboard/google/brya/variants/nereid/overridetree.cb A src/mainboard/google/brya/variants/nivviks/include/variant/ec.h A src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h A src/mainboard/google/brya/variants/nivviks/overridetree.cb 14 files changed, 179 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index ea4498a..5169324 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -53,12 +53,20 @@ select SOC_INTEL_ALDERLAKE_PCH_P select SPD_CACHE_IN_FMAP +config BOARD_GOOGLE_BASEBOARD_NISSA + def_bool n + select BOARD_GOOGLE_BRYA_COMMON + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select SOC_INTEL_ALDERLAKE_PCH_N + select SYSTEM_TYPE_LAPTOP + if BOARD_GOOGLE_BRYA_COMMON config BASEBOARD_DIR string default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK + default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES @@ -94,6 +102,8 @@ default 0x3 if BOARD_GOOGLE_ANAHERA4ES default 0x3 if BOARD_GOOGLE_VELL default 0x3 if BOARD_GOOGLE_TANIKS + default 0x0 if BOARD_GOOGLE_NIVVIKS + default 0x0 if BOARD_GOOGLE_NEREID config DRIVER_TPM_I2C_ADDR hex @@ -113,6 +123,7 @@ string default "Google_Brya" if BOARD_GOOGLE_BASEBOARD_BRYA default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK + default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA config MAINBOARD_PART_NUMBER default "Brya" if BOARD_GOOGLE_BRYA0 @@ -132,6 +143,8 @@ default "Anahera4ES" if BOARD_GOOGLE_ANAHERA4ES default "Vell" if BOARD_GOOGLE_VELL default "Taniks" if BOARD_GOOGLE_TANIKS + default "Nivviks" if BOARD_GOOGLE_NIVVIKS + default "Nereid" if BOARD_GOOGLE_NEREID config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -151,6 +164,8 @@ default "anahera4es" if BOARD_GOOGLE_ANAHERA4ES default "vell" if BOARD_GOOGLE_VELL default "taniks" if BOARD_GOOGLE_TANIKS + default "nivviks" if BOARD_GOOGLE_NIVVIKS + default "nereid" if BOARD_GOOGLE_NEREID config VBOOT select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 794bfe7..e2a4a9e 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -135,3 +135,11 @@ bool "-> Taniks" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9763E + +config BOARD_GOOGLE_NIVVIKS + bool "-> Nivviks" + select BOARD_GOOGLE_BASEBOARD_NISSA + +config BOARD_GOOGLE_NEREID + bool "-> Nereid" + select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc new file mode 100644 index 0000000..1693d2e --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-y += gpio.c + +romstage-y += memory.c +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb new file mode 100644 index 0000000..a5e2217 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + device domain 0 on + end +end diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c new file mode 100644 index 0000000..9471031 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* TODO */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* TODO */ +}; + +const struct pad_config *__weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__weak variant_gpio_override_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + /* TODO */ +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + +const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h new file mode 100644 index 0000000..a2210c6 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +/* TODO: Set the correct values */ +#define MAINBOARD_EC_SCI_EVENTS 0 +#define MAINBOARD_EC_SMI_EVENTS 0 +#define MAINBOARD_EC_S5_WAKE_EVENTS 0 +#define MAINBOARD_EC_S3_WAKE_EVENTS 0 +#define MAINBOARD_EC_S0IX_WAKE_EVENTS 0 +#define MAINBOARD_EC_LOG_EVENTS 0 + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h new file mode 100644 index 0000000..9ca9ee7 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TODO: Set the correct values */ +#define EC_SCI_GPI 0 +#define GPIO_PCH_WP 0 +#define GPIO_EC_IN_RW 0 +#define GPIO_SLP_S0_GATE 0 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/memory.c b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c new file mode 100644 index 0000000..420b366 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +const struct mb_cfg *__weak variant_memory_params(void) +{ + /* TODO */ + return NULL; +} + +bool __weak variant_is_half_populated(void) +{ + /* TODO */ + return false; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + /* TODO */ +} diff --git a/src/mainboard/google/brya/variants/nereid/include/variant/ec.h b/src/mainboard/google/brya/variants/nereid/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/nereid/include/variant/gpio.h b/src/mainboard/google/brya/variants/nereid/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb new file mode 100644 index 0000000..ee86142 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + device domain 0 on + end +end diff --git a/src/mainboard/google/brya/variants/nivviks/include/variant/ec.h b/src/mainboard/google/brya/variants/nivviks/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h b/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb new file mode 100644 index 0000000..ee86142 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/60271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5 Gerrit-Change-Number: 60271 Gerrit-PatchSet: 6 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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coreboot-gerrit January 2022