coreboot-gerrit August 2021

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Change in coreboot[master]: mb/google/dedede/var/cappy2: Disable external bypass VR
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56687 ) Change subject: mb/google/dedede/var/cappy2: Disable external bypass VR ...................................................................... mb/google/dedede/var/cappy2: Disable external bypass VR The cappy2 removed the anpec apw8738bqbi and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:194146867 BRANCH=dedede TEST=VCCIN_AUX is disable Signed-off-by: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56687 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/cappy2/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Aseda Aboagye: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb index a036e19..88b27f9 100644 --- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb @@ -28,6 +28,8 @@ }, }" + register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail + device domain 0 on device pci 15.0 on chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/56687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd Gerrit-Change-Number: 56687 Gerrit-PatchSet: 5 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/cappy2: Add Tpm2.0 device support
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56658 ) Change subject: mb/google/dedede/var/cappy2: Add Tpm2.0 device support ...................................................................... mb/google/dedede/var/cappy2: Add Tpm2.0 device support Using Tpm2.0 device instead of the Cr50 in cappy2 BUG=b:191743435 BRANCH=dedede TEST=tpm2.0 device function is ok Signed-off-by: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658 Reviewed-by: Aseda Aboagye <aaboagye(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/cappy2/overridetree.cb 1 file changed, 5 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Aseda Aboagye: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb index b11a417..a036e19 100644 --- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb @@ -4,10 +4,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | #| I2C0 | Trackpad | #| I2C1 | Digitizer | #| I2C2 | Touchscreen | @@ -15,10 +11,6 @@ #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -87,6 +79,11 @@ device i2c 1a on end end end #I2C 4 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end # Discrete TPM + end # chip drivers/pc80/tpm + end # PCH eSPI device pci 1f.3 on chip drivers/generic/alc1015 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" -- To view, visit https://review.coreboot.org/c/coreboot/+/56658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4 Gerrit-Change-Number: 56658 Gerrit-PatchSet: 6 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/broadwell: Rename `SA_DEV_ROOT`
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55528 ) Change subject: soc/intel/broadwell: Rename `SA_DEV_ROOT` ...................................................................... soc/intel/broadwell: Rename `SA_DEV_ROOT` For consistency with Haswell, rename this macro to `HOST_BRIDGE`. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/report_platform.c 5 files changed, 20 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index 9de757e..bd88195 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -29,6 +29,6 @@ * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, 0); - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c index 9b523d8..284e877 100644 --- a/src/soc/intel/broadwell/early_init.c +++ b/src/soc/intel/broadwell/early_init.c @@ -11,32 +11,32 @@ static void broadwell_setup_bars(void) { /* Set up all hardcoded northbridge BARs */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); - pci_write_config32(SA_DEV_ROOT, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); - pci_write_config32(SA_DEV_ROOT, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1); mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(SA_DEV_ROOT, PAM0, 0x30); - pci_write_config8(SA_DEV_ROOT, PAM1, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM2, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM3, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM4, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM5, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); } void systemagent_early_init(void) { const bool vtd_capable = - !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + !(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE); broadwell_setup_bars(); /* Device enable: IGD and Mini-HD */ - pci_write_config32(SA_DEV_ROOT, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); + pci_write_config32(HOST_BRIDGE, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); if (vtd_capable) { /* setup BARs: zeroize top 32 bits; set enable bit */ diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 3cf7cf3..b49023c 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -17,9 +17,7 @@ #define SA_DEV_SLOT_ROOT 0x00 #define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) -#if defined(__SIMPLE_DEVICE__) -#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) -#endif +#define HOST_BRIDGE PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f7e58af..b467dc0 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -19,7 +19,7 @@ * 1 MiB alignment and reports the TOP of the range, the base * must be calculated from the size in MiB in bits 11:4. */ - uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR); uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB); /* Subtract DMA Protected Range size if enabled */ @@ -36,8 +36,8 @@ void smm_region(uintptr_t *start, size_t *size) { - uintptr_t tseg = pci_read_config32(SA_DEV_ROOT, TSEG); - uintptr_t bgsm = pci_read_config32(SA_DEV_ROOT, BGSM); + uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG); + uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM); tseg = ALIGN_DOWN(tseg, 1 * MiB); bgsm = ALIGN_DOWN(bgsm, 1 * MiB); diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index 018ea24..7e044be 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -124,8 +124,8 @@ static void report_mch_info(void) { int i; - u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); - u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID); + u8 mch_revision = pci_read_config8(HOST_BRIDGE, PCI_REVISION_ID); const char *mch_type = "Unknown"; /* Look for string to match the revision for Broadwell U/Y */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700 Gerrit-Change-Number: 55528 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/broadwell: Drop helper functions
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55527 ) Change subject: soc/intel/broadwell: Drop helper functions ...................................................................... soc/intel/broadwell: Drop helper functions Done for consistency with Haswell in order to ease unification. Change-Id: I445f086cfcb65a6001ced3326fb9f25a4188b888 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55527 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/northbridge.c 3 files changed, 8 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 5d3992c..67b193e 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -7,6 +7,7 @@ #include <cpu/intel/haswell/haswell.h> #include <device/pci_ops.h> #include <console/console.h> +#include <device/device.h> #include <types.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> @@ -69,8 +70,13 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); + const struct device *sa_dev = pcidev_on_root(0, 0); + + /* Bit 0 is lock bit, not part of address */ + const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; + const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; + + current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_rmrr_fixup(tmp, current); } diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 331bbc7..0230f5f 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -135,7 +135,4 @@ /* System Agent identification */ u8 systemagent_revision(void); -uintptr_t sa_get_tolud_base(void); -uintptr_t sa_get_gsm_base(void); - #endif diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 838b41b..623ab70 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -21,20 +21,6 @@ return pci_read_config8(sa_dev, PCI_REVISION_ID); } -uintptr_t sa_get_tolud_base(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(sa_dev, TOLUD) & ~1; -} - -uintptr_t sa_get_gsm_base(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(sa_dev, BGSM) & ~1; -} - static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { -- To view, visit https://review.coreboot.org/c/coreboot/+/55527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I445f086cfcb65a6001ced3326fb9f25a4188b888 Gerrit-Change-Number: 55527 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell: Move MRC glue code into a subfolder
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55523 ) Change subject: nb/intel/haswell: Move MRC glue code into a subfolder ...................................................................... nb/intel/haswell: Move MRC glue code into a subfolder Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future commits will move the Broadwell MRC/refcode glue code to be in Haswell northbridge scope, so plan in advance. Tested on Asrock B85M Pro4, still boots. Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/haswell/Makefile.inc A src/northbridge/intel/haswell/haswell_mrc/Makefile.inc R src/northbridge/intel/haswell/haswell_mrc/pei_data.h R src/northbridge/intel/haswell/haswell_mrc/raminit.c 4 files changed, 13 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index f718f9a..2d1532b 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -13,17 +13,12 @@ ramstage-y += minihd.c romstage-y += memmap.c -romstage-y += raminit.c romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c -# We don't ship that, but booting without it is bound to fail -cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin -mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) -mrc.bin-position := 0xfffa0000 -mrc.bin-type := mrc - postcar-y += memmap.c +subdirs-y += haswell_mrc + endif diff --git a/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc b/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc new file mode 100644 index 0000000..bd6314c --- /dev/null +++ b/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += raminit.c + +# We don't ship that, but booting without it is bound to fail +cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin +mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) +mrc.bin-position := 0xfffa0000 +mrc.bin-type := mrc diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h similarity index 100% rename from src/northbridge/intel/haswell/pei_data.h rename to src/northbridge/intel/haswell/haswell_mrc/pei_data.h diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c similarity index 98% rename from src/northbridge/intel/haswell/raminit.c rename to src/northbridge/intel/haswell/haswell_mrc/raminit.c index 4537783..338b4d0 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -14,6 +14,8 @@ #include <device/pci_ops.h> #include <device/dram/ddr3.h> #include <northbridge/intel/haswell/chip.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> #include <smbios.h> #include <spd.h> #include <security/vboot/vboot_common.h> @@ -23,9 +25,7 @@ #include <timestamp.h> #include <types.h> -#include "raminit.h" #include "pei_data.h" -#include "haswell.h" #define MRC_CACHE_VERSION 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3 Gerrit-Change-Number: 55523 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell/gma.c: Add ULX PCI device IDs
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50137 ) Change subject: nb/intel/haswell/gma.c: Add ULX PCI device IDs ...................................................................... nb/intel/haswell/gma.c: Add ULX PCI device IDs Change-Id: Ida3d2dcdf89342b084c8e1fbf3fae7e47a7238d2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50137 Reviewed-by: Jamal Wright <Crabstorage(a)getbackinthe.kitchen> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved Jamal Wright: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index de82e3a..ccabb8c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -485,6 +485,8 @@ 0x0a06, /* ULT GT1 */ 0x0a16, /* ULT GT2 */ 0x0a26, /* ULT GT3 */ + 0x0a0e, /* ULX GT1 */ + 0x0a1e, /* ULX GT2 */ 0, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/50137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida3d2dcdf89342b084c8e1fbf3fae7e47a7238d2 Gerrit-Change-Number: 50137 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamal Wright <Crabstorage(a)getbackinthe.kitchen> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests/Makefile.inc: Add function wrapping mechanism
by Jakub Czapiga (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Julius Werner, Jan Dabros. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56719 ) Change subject: tests/Makefile.inc: Add function wrapping mechanism ...................................................................... Patch Set 3: (7 comments) File tests/Makefile.inc: https://review.coreboot.org/c/coreboot/+/56719/comment/060df53a_c096dd9b PS2, Line 123: $(OBJCOPY) $$@.orig $$(OBJCOPY_FLAGS) $$@.orig2 > nit: wouldn't it be easier to generate objcopy_wrap_flags first and then just run […] We want to add __real_<funcname> symbols only if they are present in the object file as weak symbols. We do not want to have multiple instances of __real_<funcname> e.g. for mocka and original function. https://review.coreboot.org/c/coreboot/+/56719/comment/0d11364a_77c8703b PS2, Line 126: $$$$sym) > Should put a (properly escaped) $ at the end of the regex to make sure it won't do substring matches […] Great, you noticed. It would be problematic in the future. https://review.coreboot.org/c/coreboot/+/56719/comment/60c5fd80_956a8c75 PS2, Line 126: objdump > Let's make a Makefile variable for this, same as we have for $(OBJCOPY) Done https://review.coreboot.org/c/coreboot/+/56719/comment/f0104aac_85ee56e4 PS2, Line 128: rev | awk '{ print $$$$2 }' | rev > You can just do […] Oh, it really looks simpler. Thanks https://review.coreboot.org/c/coreboot/+/56719/comment/f63a8eef_ebb57297 PS2, Line 129: .text.$$$${sym} > This should work in general, but there are rare cases where it may not (e.g. […] This makes sense. It should cover these functions. However it still will not work. See comment above :) https://review.coreboot.org/c/coreboot/+/56719/comment/4b500982_743819fc PS2, Line 129: 0 Oh I forgot to revert changes before pushing this CL. I'm sorry. > Again, in 99% of cases this offset will be 0, but to preclude problems with rare edge cases it would be better to use the real offset given by objdump. The problem with objcopy is, there is no way (or I didn't find any) to set offset and size of symbol. Symbols created by this call have address as a value, and zero as a offset/size, when function symbols created by GCC have this values swapped. https://review.coreboot.org/c/coreboot/+/56719/comment/2b76fb62_733b3a9b PS2, Line 129: before=$$$${sym} > I don't think you actually need the before=$$$${sym}? Does it not work without that? From my underst […] It is not required. But due to behavior of objcopy (described in the comment below) I added it for safety. For addr=0 and before=symbol this solution was working (probably, I am some kind of lost...). Additional info: For `--add-symbol __real_cbfs_lookup=.text.cbfs_lookup:0x7d,function,global,before=cbfs_lookup` ``` $ objdump -t src/commonlib/bsd/cbfs_private.o.orig2 | grep cbfs_lookup 0000000000000000 l d .text.cbfs_lookup 0000000000000000 .text.cbfs_lookup 0000000000000000 w F .text.cbfs_lookup 000000000000007d cbfs_lookup ``` ``` $ objdump -t src/commonlib/bsd/cbfs_private.o | grep cbfs_lookup 0000000000000000 l d .text.cbfs_lookup 0000000000000000 .text.cbfs_lookup 000000000000007d g F .text.cbfs_lookup 0000000000000000 __real_cbfs_lookup 0000000000000000 w F .text.cbfs_lookup 000000000000007d cbfs_lookup ``` For `--add-symbol` without `before=` the dump above has swapped `__real_cbfs_lookup` and `cbfs_lookup` lines. ``` $ objdump -t run | grep cbfs_lookup 00000000004025fd g F .text 0000000000000000 __real_cbfs_lookup 000000000040197e g F .text 000000000000004a cbfs_lookup ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/56719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cd0d66a17029955cbf75c8b155a7ebb7f5513aa Gerrit-Change-Number: 56719 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Mon, 02 Aug 2021 14:26:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/kconfig: detect ncurses on FreeBSD
by Angel Pons (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Martin Roth, Idwer Vollering, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56677 ) Change subject: util/kconfig: detect ncurses on FreeBSD ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56677/comment/6197b9e7_33d1247b PS4, Line 8: > Would be great to explain what this patch fixes, and/or which problem happens on FreeBSD without it. Perfect, thank you! -- To view, visit https://review.coreboot.org/c/coreboot/+/56677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e Gerrit-Change-Number: 56677 Gerrit-PatchSet: 5 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 02 Aug 2021 14:06:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: TEST: Latest JSLRVP s0ix recipe
by Maulik V Vaghela (Code Review) 02 Aug '21

02 Aug '21

Maulik V Vaghela has removed Maulik V Vaghela from this change. ( https://review.coreboot.org/c/coreboot/+/56760 ) Change subject: TEST: Latest JSLRVP s0ix recipe ...................................................................... Removed reviewer Maulik V Vaghela. -- To view, visit https://review.coreboot.org/c/coreboot/+/56760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I660815b1763da1b30d73acdb9851866c099cf953 Gerrit-Change-Number: 56760 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/brya/variants/gimble: Update overridetree for gimble
by Mark Hsieh (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: YH Lin, Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56757 ) Change subject: mb/google/brya/variants/gimble: Update overridetree for gimble ...................................................................... Patch Set 2: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/56757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f0a8c84db3fbc963797d11246c5d31b395bb744 Gerrit-Change-Number: 56757 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 02 Aug 2021 12:54:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit August 2021