Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55797 )
Change subject: soc/intel/broadwell: Replace soc/intel/common include
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Patch Set 6:
(1 comment)
Patchset:
PS5:
> i'd probably like it more to use the common soc code and header, but in this context this still soun […]
Ideally, everyone would use the code in `device/azalia_device`. I don't want Broadwell to use soc/intel/common stuff as I'm trying to unify it with Haswell/Lynxpoint
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Change subject: soc/intel/broadwell: Replace soc/intel/common include
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
i'd probably like it more to use the common soc code and header, but in this context this still sounds like a good thing to do
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50136 )
Change subject: nb/intel/haswell/gma.c: Refactor CdClk init code
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Patch Set 3:
(1 comment)
File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/50136/comment/5f63f311_f2967fc4
PS3, Line 369: * ULX defaults to 337MHz with possible override for 450MHz
: * ULT is fixed at 450MHz
: * others default to 540MHz with possible override for 450MHz
> The indentation and alingment looks strange to me.
It's aligning the numbers. I don't remember why I did it this way, but I can see why it looks strange.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55583 )
Change subject: soc/intel/broadwell/pch/pch.c: Drop unused include
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soc/intel/broadwell/pch/pch.c: Drop unused include
For some reason, this change makes ramstage slightly smaller.
Change-Id: I5564e06b797d787f0d1093bd9bd572d1ee7b2d54
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55583
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---
M src/soc/intel/broadwell/pch/pch.c
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/soc/intel/broadwell/pch/pch.c
index da13503..c2ff5b0 100644
--- a/src/soc/intel/broadwell/pch/pch.c
+++ b/src/soc/intel/broadwell/pch/pch.c
@@ -7,7 +7,6 @@
#include <device/pci_def.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
-#include <drivers/intel/gma/gma.h> /* TODO: for reproducibility purposes only */
#include <soc/rcba.h>
#include <soc/serialio.h>
#include <soc/spi.h>
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55806 )
Change subject: broadwell: Drop weak `mainboard_fill_spd_data` definition
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Patch Set 4: Code-Review+2
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Change subject: Broadwell boards: Do not assign unused SPD addresses
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Patch Set 4: Code-Review+2
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