coreboot-gerrit August 2021

coreboot-gerrit@coreboot.org

1 participants
4520 discussions

Change in coreboot[master]: mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen
by Evan Green (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Furquan Shaikh, Ren Kuo, Shou-Chieh Hsu, Karthik Ramasubramanian. Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56685 ) Change subject: mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1 Gerrit-Change-Number: 56685 Gerrit-PatchSet: 20 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 02 Aug 2021 15:20:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/tianocore: update MrChromebox UEFIPAYLOAD branch
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56569 ) Change subject: payloads/tianocore: update MrChromebox UEFIPAYLOAD branch ...................................................................... payloads/tianocore: update MrChromebox UEFIPAYLOAD branch Update tianocore branch used with default UEFIPAYLOAD option to mrchromebox/uefipayload_202107 (July 2021) branch. This branch is rebased on edk2 upstream commit 12e34cd2f7900578ee83cb01b8f1696a7bb7511b [OvmfPkg/Bhyve: clean up TPM_ENABLE remnants] vs tag edk2-stable202105. The main changes are fixes for e820 table parsing and support to disable "Above 4G decode", which is required to boot distros with bootloaders that expect to be loaded into RAM below 4G. This fixes booting with Qubes, ZorinOS, Proxmox, among others. Additionally, several commits on top of upstream have been consolidated, reworked, and/or reordered for readability and maintainability. Change-Id: I6f04fd027a0599ca6892a1376938108a2e402ac2 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56569 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 92a809a..ef3aacf 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -6,7 +6,7 @@ project_name=Tianocore project_dir=$(CURDIR)/tianocore project_git_repo=https://github.com/mrchromebox/edk2 -project_git_branch=uefipayloadpkg +project_git_branch=uefipayload_202107 upstream_git_repo=https://github.com/tianocore/edk2 build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE @@ -14,7 +14,6 @@ ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y) TAG=upstream/master else -# STABLE revision is MrChromebox's UefiPayloadPkg (ueifpayloadpkg) branch TAG=origin/$(project_git_branch) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/56569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f04fd027a0599ca6892a1376938108a2e402ac2 Gerrit-Change-Number: 56569 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56632 ) Change subject: mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed ...................................................................... mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed Some legacy devices need to have the master bit set in the PCI config due to old drivers not setting it correctly. Set the master bit if the feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE. For now, the PCI devices with the ID 110a:403e and 110a:403f needs this master bit to be set. Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/mainboard.c 1 file changed, 21 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index 4cc5490..d347567 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -4,6 +4,9 @@ #include <bootstate.h> #include <console/console.h> #include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> #include <hwilib.h> #include <i210.h> #include <soc/gpio.h> @@ -120,8 +123,25 @@ gpio_configure_pads(pads, num); } +static void mainboard_final(void *chip_info) +{ + struct device *dev; + + if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) { + /* Set Master Enable for on-board PCI devices if allowed. */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); + if (dev) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); + if (dev) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + } +} + struct chip_operations mainboard_ops = { - .init = mainboard_init, + .init = mainboard_init, + .final = mainboard_final }; BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/56632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1 Gerrit-Change-Number: 56632 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56631 ) Change subject: mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan ...................................................................... mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan Boards based on mc_ehl have, just like some mc_apl variants, legacy devices on the PCI bus which take longer to boot. In order to ensure that they will be enumerated correctly wait for them to come up before PCI scan starts. TEST=Checked that the new message is visible in the log. Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/mainboard.c 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index fc7d31f..4cc5490 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -1,12 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <hwilib.h> #include <i210.h> #include <soc/gpio.h> #include <string.h> +#include <timer.h> +#include <timestamp.h> #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 @@ -83,6 +86,31 @@ return CB_ERR; } +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -95,3 +123,5 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, }; + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/56631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd Gerrit-Change-Number: 56631 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/kukui: Add new config 'pico' in coreboot
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56691 ) Change subject: mb/google/kukui: Add new config 'pico' in coreboot ...................................................................... mb/google/kukui: Add new config 'pico' in coreboot Add new board 'pico' and set correct ram_id offset. BUG=b:194985056 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I33c37d99fa0451239bc6626e71bfddb29a11e97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56691 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 09c4205..39e6414 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -61,6 +61,7 @@ default "Cozmo" if BOARD_GOOGLE_COZMO default "Makomo" if BOARD_GOOGLE_MAKOMO default "Munna" if BOARD_GOOGLE_MUNNA + default "Pico" if BOARD_GOOGLE_PICO config DRIVER_TPM_SPI_BUS hex @@ -78,7 +79,7 @@ hex default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_MAKOMO || BOARD_GOOGLE_MUNNA default 0x20 if BOARD_GOOGLE_KAKADU || BOARD_GOOGLE_KATSU - default 0x30 if BOARD_GOOGLE_COZMO + default 0x30 if BOARD_GOOGLE_COZMO || BOARD_GOOGLE_PICO default 0x0 config BOARD_OVERRIDE_LCM_ID diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 6b5b4ce..3d5f309 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -77,3 +77,7 @@ config BOARD_GOOGLE_MUNNA bool "-> Munna" select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_PICO + bool "-> Pico" + select BOARD_GOOGLE_JACUZZI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/56691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33c37d99fa0451239bc6626e71bfddb29a11e97b Gerrit-Change-Number: 56691 Gerrit-PatchSet: 3 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Revert "mb/google/dedede/var/cret: Disable SDCard controller"
by Karthik Ramasubramanian (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Dtrain Hsu, Henry Sun, Ben Kao. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56729 ) Change subject: Revert "mb/google/dedede/var/cret: Disable SDCard controller" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I929369c9419375e74be61a4ff3e5566b0f41ce65 Gerrit-Change-Number: 56729 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ben Kao <ben.kao(a)intel.com> Gerrit-Comment-Date: Mon, 02 Aug 2021 15:04:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/cappy2: Add camera support
by Karthik Ramasubramanian (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Sunwei Li, Henry Sun, Bob Moragues, Weimin Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56647 ) Change subject: mb/google/dedede/var/cappy2: Add camera support ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3275ab408f6a03735a35eaa8025c36df09c9898c Gerrit-Change-Number: 56647 Gerrit-PatchSet: 5 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Aug 2021 15:02:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: helpers: Add GENMASK macro
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56543 ) Change subject: helpers: Add GENMASK macro ...................................................................... helpers: Add GENMASK macro The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/include/commonlib/bsd/helpers.h M src/include/device/mmio.h M src/soc/mediatek/common/pll.c M src/soc/mediatek/mt8195/dptx_hal.c M src/soc/mediatek/mt8195/include/soc/dptx_hal.h M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h M tests/commonlib/bsd/helpers-test.c 7 files changed, 33 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/helpers.h b/src/commonlib/bsd/include/commonlib/bsd/helpers.h index 376ebae..733b05a 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/helpers.h +++ b/src/commonlib/bsd/include/commonlib/bsd/helpers.h @@ -54,6 +54,9 @@ #define POWER_OF_2(x) (1ULL << (x)) +/* Set bits from `high` to `low` (inclusive). */ +#define GENMASK(high, low) (((~0ULL) << (low)) & (~0ULL >> (63 - (high)))) + #define DIV_ROUND_UP(x, y) ({ \ __typeof__(x) _div_local_x = (x); \ __typeof__(y) _div_local_y = (y); \ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 9b79d79..ca3dfa9 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -4,6 +4,7 @@ #define __DEVICE_MMIO_H__ #include <arch/mmio.h> +#include <commonlib/helpers.h> #include <endian.h> #include <types.h> @@ -130,7 +131,8 @@ #define DEFINE_BIT(name, bit) DEFINE_BITFIELD(name, bit, bit) #define _BF_MASK(name, value) \ - ((u32)((1ULL << name##_BITFIELD_SIZE) - 1) << name##_BITFIELD_SHIFT) + ((u32)GENMASK(name##_BITFIELD_SHIFT + name##_BITFIELD_SIZE - 1, \ + name##_BITFIELD_SHIFT)) #define _BF_VALUE(name, value) \ (((u32)(value) << name##_BITFIELD_SHIFT) & _BF_MASK(name, 0)) diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 539d82c..ca6226a 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -5,8 +5,6 @@ #include <soc/pll.h> #include <types.h> -#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) - void mux_set_sel(const struct mux *mux, u32 sel) { u32 mask = GENMASK(mux->mux_width - 1, 0); diff --git a/src/soc/mediatek/mt8195/dptx_hal.c b/src/soc/mediatek/mt8195/dptx_hal.c index 6c6143a..cc96cc8 100644 --- a/src/soc/mediatek/mt8195/dptx_hal.c +++ b/src/soc/mediatek/mt8195/dptx_hal.c @@ -9,6 +9,7 @@ #include <soc/dptx_reg.h> #include <string.h> #include <timer.h> +#include <types.h> #define REG_OFFSET_LIMIT 0x8000 @@ -173,21 +174,21 @@ { /* MISC0 */ mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, - out_format << 0x1, MASKBIT(2, 1)); + out_format << 0x1, GENMASK(2, 1)); switch (out_format) { case DP_COLOR_FORMAT_RGB_444: case DP_COLOR_FORMAT_YUV_444: mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, - 0, MASKBIT(6, 4)); + 0, GENMASK(6, 4)); break; case DP_COLOR_FORMAT_YUV_422: mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, - BIT(4), MASKBIT(6, 4)); + BIT(4), GENMASK(6, 4)); break; case DP_COLOR_FORMAT_YUV_420: mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, BIT(5), - MASKBIT(6, 4)); + GENMASK(6, 4)); break; default: break; @@ -592,15 +593,15 @@ { /* [7]:int, [6]:Con, [5]DisCon, [4]No-Use: UnMASK HPD Port */ mtk_dp_write_byte(mtk_dp, REG_3418_DP_TRANS_P0, - enable ? 0 : MASKBIT(7, 5), MASKBIT(7, 5)); + enable ? 0 : GENMASK(7, 5), GENMASK(7, 5)); } void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_3410_DP_TRANS_P0, - 0x8, MASKBIT(3, 0)); + 0x8, GENMASK(3, 0)); mtk_dp_write_byte(mtk_dp, REG_3410_DP_TRANS_P0, - 0xa << 4, MASKBIT(7, 4)); + 0xa << 4, GENMASK(7, 4)); DP_WRITE1BYTE(mtk_dp, REG_3410_DP_TRANS_P0 + 1, 0x55); DP_WRITE1BYTE(mtk_dp, REG_3430_DP_TRANS_P0, 0x2); @@ -643,14 +644,14 @@ void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable) { - mtk_dp_mask(mtk_dp, 0x2000, BIT(0), MASKBIT(1, 0)); + mtk_dp_mask(mtk_dp, 0x2000, BIT(0), GENMASK(1, 0)); if (enable) mtk_dp_mask(mtk_dp, 0x1014, BIT(3), BIT(3)); else mtk_dp_mask(mtk_dp, 0x1014, 0x0, BIT(3)); - mtk_dp_mask(mtk_dp, 0x2000, MASKBIT(1, 0), MASKBIT(1, 0)); + mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0)); mdelay(1); } @@ -666,7 +667,7 @@ DP_WRITE1BYTE(mtk_dp, REG_3634_AUX_TX_P0 + 1, 0x19); /* 0xd for 26M */ mtk_dp_write_byte(mtk_dp, REG_3614_AUX_TX_P0, - 0xd, MASKBIT(6, 0)); + 0xd, GENMASK(6, 0)); mtk_dp_mask(mtk_dp, REG_37C8_AUX_TX_P0, 0x01 << MTK_ATOP_EN_AUX_TX_P0_FLDMASK_POS, MTK_ATOP_EN_AUX_TX_P0_FLDMASK); @@ -681,7 +682,7 @@ dptx_hal_set_color_depth(mtk_dp, DP_COLOR_DEPTH_8BIT); mtk_dp_write_byte(mtk_dp, REG_3368_DP_ENCODER1_P0 + 1, - BIT(4), MASKBIT(5, 4)); + BIT(4), GENMASK(5, 4)); /* DPtx encoder reset all sw. */ mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, BIT(1), BIT(1)); @@ -758,7 +759,7 @@ dptx_hal_phy_setidlepattern(mtk_dp, false); mtk_dp_write_byte(mtk_dp, REG_3400_DP_TRANS_P0 + 1, - value, MASKBIT(7, 4)); + value, GENMASK(7, 4)); } void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable) diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h index b943c27..dcb1717 100644 --- a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h +++ b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h @@ -15,8 +15,6 @@ #define DP_AUX_NATIVE_WRITE 0x8 #define DP_AUX_NATIVE_READ 0x9 -#define MASKBIT(a, b) ((a > b) ? (BIT(a + 1) - BIT(b)) : (BIT(b + 1) - BIT(a))) - #define DP_WRITE1BYTE(mtk_dp, reg, u8_val) \ mtk_dp_write_byte(mtk_dp, reg, u8_val, 0xff) #define DP_WRITE2BYTE(mtk_dp, reg, u16_val) \ diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h index d2f171f..b85b9ed 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -9,8 +9,6 @@ #include <timer.h> #include <types.h> -#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) - /* GENI_OUTPUT_CTRL fields */ #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) diff --git a/tests/commonlib/bsd/helpers-test.c b/tests/commonlib/bsd/helpers-test.c index ec3f98b..324c901 100644 --- a/tests/commonlib/bsd/helpers-test.c +++ b/tests/commonlib/bsd/helpers-test.c @@ -8,6 +8,19 @@ function_called(); } +static void test_genmask(void **state) +{ + assert_int_equal(GENMASK(4, 4), 0x10); + assert_int_equal(GENMASK(4, 3), 0x18); + assert_int_equal(GENMASK(4, 0), 0x1f); + /* Edge cases */ + assert_int_equal(GENMASK(0, 0), 1); + assert_int_equal(GENMASK(31, 31), 0x80000000); + assert_int_equal(GENMASK(31, 0), 0xffffffff); + assert_int_equal(GENMASK(63, 63), 0x8000000000000000); + assert_int_equal(GENMASK(63, 0), 0xffffffffffffffff); +} + static void test_retry(void **state) { int count; @@ -34,6 +47,7 @@ int main(void) { const struct CMUnitTest tests[] = { + cmocka_unit_test(test_genmask), cmocka_unit_test(test_retry), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/56543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Gerrit-Change-Number: 56543 Gerrit-PatchSet: 7 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya: Update entries for UFC to support IMX208
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56621 ) Change subject: mb/google/brya: Update entries for UFC to support IMX208 ...................................................................... mb/google/brya: Update entries for UFC to support IMX208 1. Replace OV5675 ACPI entries with IMX208 2. Replace FW_CONFIG name 3. Add support for NVM inside UFC BUG=b:190674542 TEST=Build and boot to OS on Brya, raw capture on UFC Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56621 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 30 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index d4653bc..1f78b38 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -25,7 +25,7 @@ end field UFC 13 14 option UFC_USB 0 - option UFC_MIPI_5675 1 + option UFC_MIPI_IMX208 1 end end @@ -150,7 +150,7 @@ register "cio2_prt[0]" = "2" register "cio2_prt[1]" = "1" device generic 1 on - probe UFC UFC_MIPI_5675 + probe UFC UFC_MIPI_IMX208 end end end @@ -425,32 +425,29 @@ device i2c 2C on end end chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" + register "acpi_hid" = ""INT3478"" register "acpi_uid" = "0" register "acpi_name" = ""CAM1"" - register "chip_name" = ""Ov 5675 Camera"" + register "chip_name" = ""imx 208 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" register "ssdb.lanes_used" = "2" register "ssdb.link_used" = "1" - register "ssdb.vcm_type" = "0x0C" - register "vcm_name" = ""VCM0"" - register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "num_freq_entries" = "2" + register "link_freq[0]" = "384 * MHz" # 384 MHz + register "link_freq[1]" = "96 * MHz" # 96 MHz register "remote_name" = ""IPU0"" register "has_power_resource" = "1" #Controls - register "clk_panel.clks[0].clknum" = "IMGCLKOUT_2" - register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - register "gpio_panel.gpio[0].gpio_num" = "GPP_C3" #PP3300_FCAM_X register "gpio_panel.gpio[1].gpio_num" = "GPP_A17" #EN_UCAM_PWR register "gpio_panel.gpio[2].gpio_num" = "GPP_F20" #reset + register "gpio_panel.gpio[3].gpio_num" = "GPP_H21" #CLK_EN #_ON register "on_seq.ops_cnt" = "5" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(3, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" @@ -458,13 +455,31 @@ #_OFF register "off_seq.ops_cnt" = "4" - register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(3, 0)" register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 36 on - probe UFC UFC_MIPI_5675 + device i2c 10 on + probe UFC UFC_MIPI_IMX208 + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""INT3499"" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM1"" + register "chip_name" = ""GT24C16S"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x0E" + + device i2c 50 on + probe UFC UFC_MIPI_IMX208 end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/56621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135 Gerrit-Change-Number: 56621 Gerrit-PatchSet: 11 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya: Configure H21 as GPO and A17 as low
by Paul Fagerburg (Code Review) 02 Aug '21

02 Aug '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56655 ) Change subject: mb/google/brya: Configure H21 as GPO and A17 as low ...................................................................... mb/google/brya: Configure H21 as GPO and A17 as low As per the schematics, UFC has on card oscillator so we donot need H21 in NF1 that is IMGCLKOUT H21 is used to enable this oscialltor so configuring it as 1 A17 is configured as high while _ON method is called by driver and it is configured as low when _OFF method is called by driver. Hence coreboot should configure it as low on boot. BUG=b:190674542 Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index bb74526..fbe6323 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -37,7 +37,7 @@ /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_A17, 1, DEEP), + PAD_CFG_GPO(GPP_A17, 0, DEEP), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ @@ -299,7 +299,7 @@ /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H20, 1, DEEP), /* H21 : IMGCLKOUT2 ==> UCAM_MCLK */ - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_H21, 0, DEEP), /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Gerrit-Change-Number: 56655 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2021