Attention is currently required from: Paul Menzel, Weimin Wu.
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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56804/comment/a0456187_9894a77a
PS3, Line 9: Refer to https://review.coreboot.org/c/coreboot/+/55744.
> Please use […]
Done
https://review.coreboot.org/c/coreboot/+/56804/comment/215595c3_da2aef94
PS3, Line 15: by powerd_dbus_suspend
> This fits on one line.
Done
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Change subject: mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codec
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File src/mainboard/google/dedede/variants/cappy2/gpio.c:
https://review.coreboot.org/c/coreboot/+/56795/comment/66d8e73a_2de9ef36
PS6, Line 25: PAD_NC(GPP_D18, NONE),
> The gpio that control the main frequency signal to Realtek
GPP_D18 is configured in baseboard for I2S_MCLK, but cs42l42 not use.
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Attention is currently required from: Ryan Chuang.
Hello Ryan Chuang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/56850
to review the following change.
Change subject: vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/O
......................................................................
vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/O
Disable reading of vdram/vddq/vmddr to reduce access of i2c
to reduce DRAM init time by about 30ms.
The values were only needed by HQA report and not needed on
production units.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56850/1
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index b5b9ae1..f39023b 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -273,10 +273,12 @@
#ifndef DDR_INIT_TIME_PROFILING
print("Read voltage for %d, %d\n", p->frequency, vGet_Current_SRAMIdx(p));
print("Vcore = %d\n", dramc_get_vcore_voltage());
+#ifdef FOR_HQA_REPORT_USED
print("Vdram = %d\n", dramc_get_vmdd_voltage(p->dram_type));
print("Vddq = %d\n", dramc_get_vmddq_voltage(p->dram_type));
print("Vmddr = %d\n", dramc_get_vmddr_voltage());
#endif
+#endif
#endif
#endif
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Attention is currently required from: Ryan Chuang.
Hello Ryan Chuang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/56849
to review the following change.
Change subject: vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count
......................................................................
vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM
frequency counts to reduce DRAM initialization time by about 100ms.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/56849/1
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index b5de592..b5b9ae1 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -1882,6 +1882,9 @@
ett_fix_freq = 1; /* only 1600 & 4266 */
#endif
+ if (CONFIG(MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT))
+ ett_fix_freq = 0x1; // 4266, 1600
+
if (ett_fix_freq != 0xff)
gAndroid_DVFS_en = FALSE;
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56845
to look at the new patch set (#3).
Change subject: payloads/libpayload: add MTK_TIMER_V2 config
......................................................................
payloads/libpayload: add MTK_TIMER_V2 config
The timer structure (in particular, the offset to memory addresses)
on recent MTK SoCs for example MT8195 has been changed.
BUG=b:195274787
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac
---
M payloads/libpayload/drivers/timer/Kconfig
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/56845/3
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