Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56906 )
Change subject: soc/mediatek: revise the dependency of DVFS config options
......................................................................
soc/mediatek: revise the dependency of DVFS config options
The MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT only makes sense if DVFS
is enabled (e.g., MEDIATEK_DRAM_DVFS) so we should change it to
depend on that instead of selecting DVFS.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: Ib81e4e48e863616ed1e36cd5c0000f4e2cfb5456
---
M src/soc/mediatek/common/Kconfig
M src/soc/mediatek/mt8192/Kconfig
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/56906/1
diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index 7411e48..ab24617 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -17,7 +17,7 @@
config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT
bool
default y
- select MEDIATEK_DRAM_DVFS
+ depends on MEDIATEK_DRAM_DVFS
help
This options limit DRAM frequency calibration count from total 7 to 3,
other frequency will directly use the low frequency shu result.
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig
index 21dcc7c..94e4bd3 100644
--- a/src/soc/mediatek/mt8192/Kconfig
+++ b/src/soc/mediatek/mt8192/Kconfig
@@ -10,6 +10,7 @@
select HAVE_DEBUG_RAM_SETUP
select HAVE_UART_SPECIAL
select SOC_MEDIATEK_COMMON
+ select MEDIATEK_DRAM_DVFS
if SOC_MEDIATEK_MT8192
--
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52843 )
Change subject: soc/intel/skylake: Clean up FSP chipset lockdown configuration
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
> Tested? (I don't expect any issues but I could sleep better ;) )
Not tested, but I do think the change is fairly small and easy to review.
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Change subject: soc/intel/alderlake: Clean up FSP chipset lockdown configuration
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/52846/comment/7ffcec4c_c18e7f87
PS7, Line 143: uint8_t
> bool
Done
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Change subject: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/52845/comment/6922d886_3a9b7a6e
PS7, Line 106: uint8_t
> bool
Done
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Change subject: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/52844/comment/dcc2cc99_ca99615a
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Hello build bot (Jenkins), Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: soc/intel/alderlake: Clean up FSP chipset lockdown configuration
......................................................................
soc/intel/alderlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-else-clause.
Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 5 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/52846/8
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Hello build bot (Jenkins), Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52845
to look at the new patch set (#8).
Change subject: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
......................................................................
soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-else-clause.
Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/jasperlake/fsp_params.c
1 file changed, 5 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/52845/8
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