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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56152 )
Change subject: soc/intel/alderlake: Call cpu_fill_code_cache() from bootblock
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56152/comment/ba729cea_b8d3adb2
PS1, Line 12: perform
> performs
Ack
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56152
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Call cpu_fill_code_cache() from bootblock
......................................................................
soc/intel/alderlake: Call cpu_fill_code_cache() from bootblock
Make use of cpu_fill_code_cache() helper function to perform cache
stress test.
TEST=This function performs cache stress test if SOC_INTEL_CAR_DEBUG
is selected.
Change-Id: If0708737ce000eddd8d36876d195712d63c3915e
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/alderlake/bootblock/bootblock.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/56152/2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56152 )
Change subject: soc/intel/alderlake: Call cpu_fill_code_cache() from bootblock
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56152/comment/194ba3ba_1ea6204d
PS1, Line 12: perform
performs
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Hello build bot (Jenkins), Wisley Chen,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:B
......................................................................
mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:B
Add SPD support to lantis for MT53E512M32D1NP-046 WT:B
BUG=b:196161820
BRANCH=firmware-dedede-13606.B
TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage
Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98
---
M src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc
M src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/56909/2
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Attention is currently required from: Wisley Chen.
Hello Wisley Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/56909
to review the following change.
Change subject: mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:B
......................................................................
mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:B
Add SPD support to lantis for MT53E512M32D1NP-046 WT:B
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage
Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98
---
M src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc
M src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/56909/1
diff --git a/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc
index f6282bf..a934428 100644
--- a/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc
@@ -2,4 +2,4 @@
## This is an auto-generated file. Do not edit!!
SPD_SOURCES =
-SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR
+SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B
diff --git a/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt
index 856d016..e8ec694 100644
--- a/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt
@@ -2,3 +2,4 @@
MT53E512M32D2NP-046 WT:E 0 (0000)
H9HCNNNBKMMLXR-NEE 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
+MT53E512M32D1NP-046 WT:B 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt
index 1bcd3da..09ed381 100644
--- a/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt
@@ -1,14 +1,4 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.inc and dram_id.generated.txt by running the
-# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
-# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
-
-# Part Name
MT53E512M32D2NP-046 WT:E
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
+MT53E512M32D1NP-046 WT:B
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Hello Ryan Chuang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/56907
to review the following change.
Change subject: vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore setting
......................................................................
vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore setting
Remove the unnecessary Vcore setting for the DVFS feature.
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: If3c28e57a559a7ec04319c1a489138817e44ec4a
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56907/1
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index f39023b..501f9d3 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -229,8 +229,9 @@
}
#endif
- if (vcore)
- dramc_set_vcore_voltage(vcore);
+ if (CONFIG(MEDIATEK_DRAM_DVFS))
+ if (vcore)
+ dramc_set_vcore_voltage(vcore);
#if defined(DRAM_HQA)
if (vio18)
@@ -1884,7 +1885,7 @@
ett_fix_freq = 1; /* only 1600 & 4266 */
#endif
- if (CONFIG(MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT))
+ if (!CONFIG(MEDIATEK_DRAM_DVFS))
ett_fix_freq = 0x1; // 4266, 1600
if (ett_fix_freq != 0xff)
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