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Change subject: mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56881/comment/a92aedc9_e8c73a52
PS5, Line 7: Add support
> I think support was there already :) what you did is to modify the DIMM type to memory_down_spd_info […]
Done
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Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56881
to look at the new patch set (#6).
Change subject: mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
......................................................................
mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
DDR5 Maple ridge SKU (Board ID 0x16) uses a Memory down DIMM
configuration.
TEST=Boot DDR5 MR SKU to OS.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/adlrvp/spd/Makefile.inc
A src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex
3 files changed, 34 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/56881/6
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Sudheer Amrabadi has uploaded a new patch set (#62) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50581 )
Change subject: src/mainboard/herobrine: Initialize SPI FW for EC and TPM
......................................................................
src/mainboard/herobrine: Initialize SPI FW for EC and TPM
Initialize SPI firmware for EC and H1/TPM instances.
Load QUP FW in respective Serial Engines.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c
Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org>
---
M src/mainboard/google/herobrine/Kconfig
M src/mainboard/google/herobrine/bootblock.c
M src/soc/qualcomm/common/spi.c
3 files changed, 13 insertions(+), 1 deletion(-)
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Change subject: soc/qualcomm/common: clock: Add support for common clock driver
......................................................................
soc/qualcomm/common: clock: Add support for common clock driver
The clock driver supports configuring the general purpose PLLs,
configuring the root clock generator (RCG), enable clock branch, enable
gdsc and also the block resets.
The common clock driver exposes PLL configuration functions and also
different Agera PLL enable functions for the CPU PLLs.
While at it, the common driver also supports reset of subsystems like
AOP and SHRM.
SC7180 clock driver is also refactored to use the common clock
driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39
Signed-off-by: Taniya Das <tdas(a)codeaurora.org>
---
A src/soc/qualcomm/common/clock.c
A src/soc/qualcomm/common/include/soc/clock_common.h
M src/soc/qualcomm/sc7180/Makefile.inc
M src/soc/qualcomm/sc7180/clock.c
M src/soc/qualcomm/sc7180/include/soc/clock.h
5 files changed, 503 insertions(+), 355 deletions(-)
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Change subject: qualcomm/sc7180: Cleanups for drivers with common clock
......................................................................
qualcomm/sc7180: Cleanups for drivers with common clock
As we move to use the common clock driver, the sc7180 clock driver,
watchdog and display drivers requires few cleanups, thus update the
impacted drivers.
Earlier the display client is expected to provide 2n divider value,
as the divider value in register is in form "2n-1".
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;
The older convention in the upcoming patches would be replaced with the
common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated.
mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0;
To accommodate impacting the functionality, the half_divider is taken
care in the clock driver.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66
Signed-off-by: Taniya Das <tdas(a)codeaurora.org>
---
M src/soc/qualcomm/sc7180/clock.c
M src/soc/qualcomm/sc7180/display/dsi_phy.c
M src/soc/qualcomm/sc7180/include/soc/clock.h
M src/soc/qualcomm/sc7180/watchdog.c
4 files changed, 65 insertions(+), 58 deletions(-)
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
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to review the following change.
Change subject: [WIP]nb/intel/sandybridge: Use a chipset devicetree
......................................................................
[WIP]nb/intel/sandybridge: Use a chipset devicetree
This allows to reduce boilerplate a lot
Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/lenovo/x220/devicetree.cb
M src/northbridge/intel/sandybridge/Kconfig
A src/northbridge/intel/sandybridge/chipset.cb
3 files changed, 73 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/56912/1
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 53eb23a..ee3b97e 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -15,24 +15,10 @@
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
- device cpu_cluster 0 on
- chip cpu/intel/model_206ax
- # Magic APIC ID to locate this chip
- device lapic 0 on end
- device lapic 0xacac off end
-
- register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
- register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3)
- register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7)
- end
- end
-
device domain 0 on
subsystemid 0x17aa 0x21db inherit
- device pci 00.0 on end # host bridge
- device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # vga controller
+ device ref igd on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
@@ -60,34 +46,28 @@
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 19.0 on
+ device ref gbe on
subsystemid 0x17aa 0x21ce
end # Intel Gigabit Ethernet
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2 (wlan)
- device pci 1c.2 on end # PCIe Port #3
- device pci 1c.3 on
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref rp1 on end # PCIe Port #1
+ device ref rp2 on end # PCIe Port #2 (wlan)
+ device ref rp3 on end # PCIe Port #3
+ device ref rp4 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end # PCIe Port #4
- device pci 1c.4 on
+ device ref rp5 on
chip drivers/ricoh/rce822
register "sdwppol" = "1"
register "disable_mask" = "0x87"
device pci 00.0 on end
end
end # PCIe Port #5 (SD)
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on #LPC bridge
+ device ref rp7 on end # PCIe Port #7
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_b off end # PCI bridge
+ device ref lpc on #LPC bridge
chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy
register "backlight_enable" = "0x01"
@@ -139,8 +119,8 @@
register "wwan_gpio_lvl" = "0"
end
end # LPC bridge
- device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
@@ -153,8 +133,7 @@
device i2c 5f on end
end
end # SMBus
- device pci 1f.5 off end # SATA Controller 2
- device pci 1f.6 on end # Thermal
+ device ref thermal on end # Thermal
end
end
end
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 501ca9f..5c76b7b 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -9,6 +9,10 @@
if NORTHBRIDGE_INTEL_SANDYBRIDGE
+config CHIPSET_DEVICETREE
+ string
+ default "northbridge/intel/sandybridge/chipset.cb"
+
config SANDYBRIDGE_VBOOT_IN_ROMSTAGE
bool
default n
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
new file mode 100644
index 0000000..59ea0b0
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0 on end
+ device lapic 0xacac off end
+
+ register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
+ register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3)
+ register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x17aa 0x21db inherit
+
+ device pci 00.0 alias hb on end # host bridge
+ device pci 01.0 alias peg10 off end # PEG10
+ device pci 01.1 alias peg11 off end # PEG11
+ device pci 01.2 alias peg12 off end # PEG12
+ device pci 02.0 alias igd off end # vga controller
+ device pci 04.0 alias dev4 off end # Device 4
+ device pci 06.0 alias peg60 off end # PEG60
+
+ chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH
+ device pci 14.0 alias xhci off end # USB 3.0 Controller
+ device pci 16.0 alias mei1 off end # Management Engine Interface 1
+ device pci 16.1 alias mei2 off end # Management Engine Interface 2
+ device pci 16.2 alias me_ide_r off end # Management Engine IDE-R
+ device pci 16.3 alias me_kt off end # Management Engine KT
+ device pci 19.0 alias gbe off end # Intel Gigabit Ethernet
+ device pci 1a.0 alias ehci2 off end # USB2 EHCI #2
+ device pci 1b.0 alias hda off end # High Definition Audio
+ device pci 1c.0 alias rp1 off end # PCIe Port #1
+ device pci 1c.1 alias rp2 off end # PCIe Port #2
+ device pci 1c.2 alias rp3 off end # PCIe Port #3
+ device pci 1c.3 alias rp4 off end # PCIe Port #4
+ device pci 1c.4 alias rp5 off end # PCIe Port #5
+ device pci 1c.5 alias rp6 off end # PCIe Port #6
+ device pci 1c.6 alias rp7 off end # PCIe Port #7
+ device pci 1c.7 alias rp8 off end # PCIe Port #8
+ device pci 1d.0 alias ehci1 off end # USB2 EHCI #1
+ device pci 1e.0 alias pci_b off end # PCI bridge
+ device pci 1f.0 alias lpc off end # LPC bridge
+ device pci 1f.2 alias sata1 off end # SATA Controller 1
+ device pci 1f.3 alias smbus off end # SMBus
+ device pci 1f.5 alias sata2 off end # SATA Controller 2
+ device pci 1f.6 alias thermal off end # Thermal
+ end
+ end
+end
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Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56380 )
Change subject: mb/google/octopus/var/phaser: Change IRQ trigger method to level
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56380/comment/eb01f8e3_d447c259
PS4, Line 14:
> Is that commit 3b879f46b49b756b4f6e851d97677a821e11ce1d?
The commit above is for G2Touch not for Elan so might not be relevant. Partners mentioned that the original Elan section here was copied from reference design and they never build product with Elan touchscreen before.
And the feedback from vendor side mentioned, level or edge triggering should be all workable but level would be recommended from vendor side.
Patchset:
PS4:
Hi Joey, please address comments from reviewer - Paul. Thanks.
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Change subject: cezanne/fw.cfg: Remove two FWs from amdfw.rom
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS8:
> Yeah, that's my thought. […]
Add a comment is fw.cfg
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