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Change subject: elogtool: add "clear" command
......................................................................
Patch Set 3:
(3 comments)
File src/drivers/elog/elog.c:
https://review.coreboot.org/c/coreboot/+/56883/comment/f1bf7dce_12d5df4f
PS3, Line 825:
indent to (
File util/cbfstool/elogtool.c:
https://review.coreboot.org/c/coreboot/+/56883/comment/c2c2ff5e_2d933de5
PS2, Line 166: NULL
> added. […]
hmm ... good point ... separate inputs and outputs may be a useful feature, especially for testing... but possibly in the future?
I think we can add it down the road
File util/cbfstool/elogtool.c:
https://review.coreboot.org/c/coreboot/+/56883/comment/1d01029f_465b0fe3
PS3, Line 200: {
: buffer_delete(&buf);
: return ret;
: }
you can drop the repeated code by using a goto
{
...
if (ret != 0)
goto exit;
...
exit:
buffer_delete(&buf);
return ret;
}
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Change subject: include/bcd: move bcd code to commonlib/bsd/include
......................................................................
Patch Set 1:
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/bcd.h:
https://review.coreboot.org/c/coreboot/+/56904/comment/68aa671b_65da3106
PS1, Line 1: GPL-2.0-only
Needs changed to BSD
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Change subject: include/bcd: move bcd code to commonlib/bsd/include
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Yes, let's get an approval from the original author. […]
I think it's OK since as Ricardo mentions, this code existed in mosys under a BSD license before coreboot (going back to 2012).... at least the bin2bcd part.
I'm no lawyer tho, so may be best to wait.
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56503
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Change subject: soc/intel/alderlake: Processor hang while hot plug unplug of TBT Device
......................................................................
soc/intel/alderlake: Processor hang while hot plug unplug of TBT Device
BIOS should execute TBT PCIe RP RTD3 flow based on the value
TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
BIT30 in TBT FW version is not set.
BUG=b:194880254
Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/soc/intel/alderlake/acpi/tcss.asl
M src/soc/intel/alderlake/acpi/tcss_dma.asl
2 files changed, 10 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/56503/6
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Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52349 )
Change subject: mb/system76/darp7: Add System76 Darter Pro 7
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/system76/darp7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/52349/comment/1e4e2cc5_fc4fa9c4
PS9, Line 146: device ref tbt_dma0 on # J_TYPEC2
I assume I have something misconfigured, since in dmesg I see these:
pci 0000:00:07.0: DPC: RP PIO log size 0 is invalid
thunderbolt: probe of 0000:00:0d.2 failed with error -110
Although, I have no TBT devices to test with.
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Change subject: soc/intel/common: Add TGL-H PCI IDs
......................................................................
Set Ready For Review
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Hello build bot (Jenkins), Wisley Chen,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:B
......................................................................
mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:B
Add SPD support to lantis for MT53E512M32D1NP-046 WT:B
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage
Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98
Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc
M src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/56909/3
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Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
......................................................................
Patch Set 64:
(2 comments)
File src/drivers/spi/spi_flash.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126066):
https://review.coreboot.org/c/coreboot/+/50586/comment/980b844b_2c6bc8cb
PS64, Line 541: while (1)
suspect code indent for conditional statements (24, 24)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126066):
https://review.coreboot.org/c/coreboot/+/50586/comment/d7accad6_55760d3e
PS64, Line 562: while (1)
suspect code indent for conditional statements (24, 24)
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