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Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56750 )
Change subject: vc/google/chromeos: Add support for new SAR tables revisions
......................................................................
Patch Set 17:
(2 comments)
File src/include/sar.h:
https://review.coreboot.org/c/coreboot/+/56750/comment/bbe04b66_cb174827
PS17, Line 21: struct wifi_sar_delta_table {
: uint8_t version;
: union {
: struct {
: uint8_t power_max_2400mhz;
: uint8_t power_chain_a_2400mhz;
: uint8_t power_chain_b_2400mhz;
: uint8_t power_max_5200mhz;
: uint8_t power_chain_a_5200mhz;
: uint8_t power_chain_b_5200mhz;
: } __packed group_rev0[SAR_NUM_WGDS_GROUPS];
: struct {
: uint8_t power_max_2400mhz;
: uint8_t power_chain_a_2400mhz;
: uint8_t power_chain_b_2400mhz;
: uint8_t power_max_5200mhz;
: uint8_t power_chain_a_5200mhz;
: uint8_t power_chain_b_5200mhz;
: uint8_t power_max_6000mhz;
: uint8_t power_chain_a_6000mhz;
: uint8_t power_chain_b_6000mhz;
: } __packed group_rev1[SAR_NUM_WGDS_GROUPS];
: } __packed;
: } __packed;
> I think we should hide the differences of different revisions on the SAR file generation side so tha […]
This think this will be better approach. I will update all the current implementation as per the suggestion.
File src/vendorcode/google/chromeos/sar.c:
https://review.coreboot.org/c/coreboot/+/56750/comment/b6bc7e9e_cb53301c
PS17, Line 138: if (CONFIG(USE_SAR)) {
: sar_limits->sar_table->version = 0;
: sar_limits->sar_table->sar_enable = CONFIG(SAR_ENABLE);
: sar_limits->sar_table->dsar_enable = CONFIG(DSAR_ENABLE);
: sar_limits->sar_table->dsar_set_num = CONFIG_DSAR_SET_NUM;
: }
> I like the fact that you are trying to fix the problems with the original representation of SAR tabl […]
I will update the logic to remove USE_SAR_V2.
Only possible SAR file size with the older implementation is 119 and 81.
As of now, none of the revision combination leads to this size of binary, I will recheck once I address the review comments. I think we can also have some fallback mechanism to use the other version incase if the decoding fails with revision 0.
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Maciej Pijanowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57072 )
Change subject: src/lib/fmap.c: use le*toh() functions where needed
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This patch was already posted here: https://review.coreboot.org/c/coreboot/+/55038
We should use this one
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Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57088
to look at the new patch set (#2).
Change subject: cpu/intel: Make doubly sure we don't write to IA32_FEATURE_CTRL if its lock bit is set on a reset.
......................................................................
cpu/intel: Make doubly sure we don't write to IA32_FEATURE_CTRL if its
lock bit is set on a reset.
The lock bit in this MSR is preserved across resets,
Change-Id: Id21cc304b1e1e2871b684e287713af1c6a603efe
Signed-off-by: Darius Goad <mszoopers(a)protonmail.com>
---
M src/cpu/intel/model_1067x/mp_init.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/57088/2
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Change subject: cpu/intel: Make doubly sure we don't write to IA32_FEATURE_CTRL if its lock bit is set.
......................................................................
Abandoned
Didn't realize I had to use my legal name.
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Name of user not set #1003839 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57088 )
Change subject: cpu/intel: Make doubly sure we don't write to IA32_FEATURE_CTRL if its lock bit is set.
......................................................................
cpu/intel: Make doubly sure we don't write to IA32_FEATURE_CTRL if its
lock bit is set.
Change-Id: Id21cc304b1e1e2871b684e287713af1c6a603efe
Signed-off-by: Darius Goad <mszoopers(a)protonmail.com>
---
M src/cpu/intel/model_1067x/mp_init.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/57088/1
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index fd6a82a..7b26875 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -59,6 +59,8 @@
printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
printk(BIOS_DEBUG, "SMRR status: %senabled\n",
ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+ smm_relocate();
+ return;
} else {
if (!CONFIG(SET_IA32_FC_LOCK_BIT))
printk(BIOS_INFO,
--
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Name of user not set #1003839 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57087 )
Change subject: cpu/intel: Make doubly sure we don't write to IA32_FEATURE_CTRL if its lock bit is set.
......................................................................
cpu/intel: Make doubly sure we don't write to IA32_FEATURE_CTRL
if its lock bit is set.
Change-Id: I6c13727efe845c32ead57d7e0fb2ad3239dd9f70
Signed-off-by: Melody Goad <mszoopers(a)protonmail.com>
---
M src/cpu/intel/model_1067x/mp_init.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/57087/1
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index fd6a82a..7b26875 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -59,6 +59,8 @@
printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
printk(BIOS_DEBUG, "SMRR status: %senabled\n",
ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+ smm_relocate();
+ return;
} else {
if (!CONFIG(SET_IA32_FC_LOCK_BIT))
printk(BIOS_INFO,
--
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57042 )
Change subject: soc/mediatek/mt8195: add HDMI low power setting
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
@hung-te, could we merge this patch?
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Change subject: mb/google/brya: Enable SaGv support
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Is this stable on all board revisions?
Yes, verified it on Brya P1 and P2 boards.
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