coreboot-gerrit August 2021

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Change in coreboot[master]: soc/intel/tigerlake: Add PCH-H chipset devicetree
by Tim Wawrzynczak (Code Review) 23 Aug '21

23 Aug '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56945 ) Change subject: soc/intel/tigerlake: Add PCH-H chipset devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7 Gerrit-Change-Number: 56945 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 23 Aug 2021 01:57:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add TGL-H power limits
by Tim Wawrzynczak (Code Review) 23 Aug '21

23 Aug '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56943 ) Change subject: soc/intel/tigerlake: Add TGL-H power limits ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/tigerlake/chip.h: https://review.coreboot.org/c/coreboot/+/56943/comment/0ab39762_1ecc6f9e PS2, Line 26: /* The first two are for TGL-U */ : #define POWER_LIMITS_U_2_CORE 0 : #define POWER_LIMITS_U_4_CORE 1 : #define POWER_LIMITS_Y_2_CORE 2 : #define POWER_LIMITS_Y_4_CORE 3 : #define POWER_LIMITS_H_6_CORE 4 : #define POWER_LIMITS_H_8_CORE 5 : #define POWER_LIMITS_MAX 6 Mind making this an enum now? -- To view, visit https://review.coreboot.org/c/coreboot/+/56943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Gerrit-Change-Number: 56943 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 23 Aug 2021 01:56:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Add TGL-H CPUID
by Tim Wawrzynczak (Code Review) 23 Aug '21

23 Aug '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56942 ) Change subject: soc/intel: Add TGL-H CPUID ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6 Gerrit-Change-Number: 56942 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 23 Aug 2021 01:54:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Align comments in overridetree
by David Hendricks (Code Review) 23 Aug '21

23 Aug '21

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57071 ) Change subject: mb/google/brya/var/brya0: Align comments in overridetree ...................................................................... mb/google/brya/var/brya0: Align comments in overridetree Change-Id: Id3eb18cae2dd9a7b148bc9f3dcaf387f35dbd2fb Fixes: 312fb716 ("mb/google/brya: Add ALC1019_NAU88L25B support") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57071 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index f053eb6..3e02642 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -204,21 +204,21 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" register "jkdet_enable" = "1" register "jkdet_pull_enable" = "0" - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 register "sar_threshold_num" = "4" register "sar_threshold[0]" = "0x0c" register "sar_threshold[1]" = "0x1c" register "sar_threshold[2]" = "0x38" register "sar_threshold[3]" = "0x60" register "sar_hysteresis" = "1" - register "sar_voltage" = "0" # VDDA - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us - register "short_key_debounce" = "2" # 100ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "7" # 512ms + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms device i2c 1a on probe AUDIO ALC1019_NAU88L25B_I2S end -- To view, visit https://review.coreboot.org/c/coreboot/+/57071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3eb18cae2dd9a7b148bc9f3dcaf387f35dbd2fb Gerrit-Change-Number: 57071 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86: Implement cpu_info in C code
by David Hendricks (Code Review) 23 Aug '21

23 Aug '21

Attention is currently required from: Arthur Heymans. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57049 ) Change subject: arch/x86: Implement cpu_info in C code ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7396b8429e29739e18a189dacea3a76e571cd58 Gerrit-Change-Number: 57049 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 22 Aug 2021 23:15:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: AGESA f15tn: Fix building IDS tracing support
by David Hendricks (Code Review) 23 Aug '21

23 Aug '21

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53986 ) Change subject: AGESA f15tn: Fix building IDS tracing support ...................................................................... AGESA f15tn: Fix building IDS tracing support Also add a config file to ensure the code gets build-tested. Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986 Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A configs/config.asus_a88xm-e.agesa_debug M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c M src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c M src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c M src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c 17 files changed, 44 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/configs/config.asus_a88xm-e.agesa_debug b/configs/config.asus_a88xm-e.agesa_debug new file mode 100644 index 0000000..c4ec6c66 --- /dev/null +++ b/configs/config.asus_a88xm-e.agesa_debug @@ -0,0 +1,7 @@ +CONFIG_VENDOR_ASUS=y +CONFIG_BOARD_ASUS_A88XM_E=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_IDS_TRACING_ENABLED=y +CONFIG_AGESA_EXTRA_TIMESTAMPS=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_DEBUG_RESOURCES=y diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c index 1660c49..8735dac 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c @@ -147,10 +147,8 @@ MmioRange[MmioPair].RangeNum = MmioPair; MmioRange[MmioPair].Modified = FALSE; IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); - IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Base & 0xFFFFFFFF, - (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, "%016llx %016llx", MmioRange[MmioPair].Base, + MmioRange[MmioPair].Limit); IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N", @@ -164,10 +162,8 @@ NewMmioRange.Base = AmdAddMmioParams.BaseAddress; NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length + 0x10000; NewMmioRange.Attribute = AmdAddMmioParams.Attributes; - IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF, - NewMmioRange.Base & 0xFFFFFFFF, - (NewMmioRange.Limit >> 32) & 0xFFFFFFFF, - NewMmioRange.Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, "req %016llx %016llx\n", NewMmioRange.Base, + NewMmioRange.Limit); for (ConfMapRange = 0; ConfMapRange < CONF_MAP_NUM; ConfMapRange++) { PciAddress.Address.Register = (CONF_MAP_RANGE_0 + ConfMapRange * 4); LibAmdPciRead (AccessWidth32, PciAddress, &ConfMapRegister, &(AmdAddMmioParams.StdHeader)); @@ -298,10 +294,8 @@ PciAddress.Address.Function = FUNC_1; for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) { IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); - IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Base & 0xFFFFFFFF, - (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, "%016llx %016llx", MmioRange[MmioPair].Base, + MmioRange[MmioPair].Limit); IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N", diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c index 5cb2adc..ce4c8d1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c @@ -155,7 +155,7 @@ IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); + IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (char *)&UserOptions.VersionString); AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); ASSERT (ResetParams != NULL); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c index b8716f2..747b283 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c @@ -165,7 +165,7 @@ PCI_ADDR PciAddress; UINTN Index; S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); - IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n"); while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { switch (*(UINT16 *) S3SaveTableRecordPtr) { case SAVE_STATE_IO_WRITE_OPCODE: diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c index eaebdb1..94f5e12 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c @@ -268,7 +268,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); IDS_HDT_CONSOLE (S3_TRACE, "\n"); ); @@ -333,7 +333,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -409,7 +409,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -481,7 +481,7 @@ SaveOffsetPtr->OpCode = OpCode; SaveOffsetPtr->Length = InformationLength; S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %p\n", Information); ); LibAmdMemCopy ( (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c index ba45bd7..da2bf93 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c @@ -139,7 +139,7 @@ FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr; ASSERT (FchParams != NULL); - IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = %p\n", AgesaStatus, FchParams); // Load private data block with default *FchParams = InitEnvCfgDefault; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c index 3d8f093..9be08b7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c @@ -71,7 +71,7 @@ FchParams = (FCH_RESET_DATA_BLOCK *) AllocHeapParams.BufferPtr; ASSERT (FchParams != NULL); - IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = %p\n", AgesaStatus, FchParams); *FchParams = InitResetCfgDefault; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 7f701f0..69137a0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -473,7 +473,7 @@ Index += 4; break; case 4: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); + IDS_HDT_CONSOLE (GNB_TRACE, "%016llx", *(UINT64 *) ((UINT8 *) Buffer + Index)); Index += 8; break; default: diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c index 8befb2c..05b11fe 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c @@ -223,7 +223,7 @@ ); IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); + IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%llx\n", Gfx->UmaInfo.UmaBase); IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index 422cbae..7cb69fd 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -895,7 +895,7 @@ ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n"); for (Index = 0; Index < StateArray->ucNumEntries; Index++) { - IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 + IDS_HDT_CONSOLE (GFX_MISC, " State #%ld\n", Index + 1 ); IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification @@ -922,7 +922,7 @@ for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) { UINT32 Sclk; Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16); - IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n", + IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", @@ -951,7 +951,7 @@ for (Index = 0; Index < VceStateTable->numEntries; Index++) { SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F; EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex; - IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%ld\n", Index ); if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) { IDS_HDT_CONSOLE (GFX_MISC, " Disable\n"); @@ -973,7 +973,7 @@ IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n"); for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) { EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex; - IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n", VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c index 8b388d5..15c0679 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c @@ -337,7 +337,7 @@ ASSERT (GnbHandle != NULL); GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader); if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) { - IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); + IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %llx, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); return; } GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c index 8c580a0..d5dcdad 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c @@ -888,7 +888,7 @@ IN AMD_CONFIG_PARAMS *StdHeader ) { - UINTN Index; + UINT32 Index; IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); for (Index = 0; Index < 4; Index++) { @@ -945,7 +945,7 @@ ); IDS_HDT_CONSOLE ( NB_MISC, - " VCE Flags[ % d] - 0x % 02x\n", + " VCE Flags[%d] - 0x%02x\n", Index, PpFuseArray->VceFlags[Index] ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c index b6b98e0..1eb8d9b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c @@ -292,7 +292,7 @@ Entry = Entry + 4; break; default: - IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n", *Entry); ASSERT (FALSE); } } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c index 84a02d1..b67d3c5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c @@ -578,7 +578,7 @@ BaseAddress |= Value; if ((BaseAddress & 0xfffffffffffffffe) != 0x0) { - IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %llx for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader); } else { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 9b7bcbd..e839a1d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -557,7 +557,10 @@ EngineList->Type.Port.Address.Address.Device, EngineList->Type.Port.Address.Address.Function ); - IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Compliance Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkComplianceMode); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Safe Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkSafeMode); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, SB Link - %u\n", EngineList->Type.Port.PortData.MiscControls.SbLink); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, CLK PM Support - %u\n", EngineList->Type.Port.PortData.MiscControls.ClkPmSupport); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", @@ -737,7 +740,7 @@ EngineDescriptor->EngineData.EndLane ); if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n MiscControls - 0x%02x\n" , + IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n Compliance Mode - %d\n Safe Mode - %d\n SB link - %d\n CLK PM Support - %d\n" , ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, @@ -746,8 +749,10 @@ ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkComplianceMode, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkSafeMode, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.ClkPmSupport ); } if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { @@ -785,7 +790,7 @@ for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); - IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", + IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %ld\n", ComplexDescriptor->SocketId, NumberOfEngines ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c index 2a40c09..9873154 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c @@ -167,7 +167,7 @@ for (Index = 0; Index < 4; Index++) { if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); + IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; } } @@ -177,7 +177,7 @@ } LaneBitmapForPllOffInL1 = 0; for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); + IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Final Latency %d\n", Index, LaneGroupExitLatency[Index]); if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c index 1030d7a..eaf5b49 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c @@ -442,7 +442,7 @@ AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %p\n", Socket, Channel, Dimm, SpdParam.Buffer); #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) AgesaCustomMemoryProfileSPD(SpdParam.Buffer); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/53986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Gerrit-Change-Number: 53986 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: AGESA f15tn: Hook up IDS options to Kconfig
by David Hendricks (Code Review) 23 Aug '21

23 Aug '21

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53985 ) Change subject: AGESA f15tn: Hook up IDS options to Kconfig ...................................................................... AGESA f15tn: Hook up IDS options to Kconfig IDS (Integrated Debug Services) options are meant to be enabled when one wants to debug AGESA. Since they are compile-time options, using Kconfig is the logical choice. Currently, none of the options builds. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and Asus A88XM-E does not change. Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M src/cpu/amd/agesa/family15tn/Kconfig M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f15tn/OptionsIds.h 3 files changed, 62 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 70f71ed..8c52e9a 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -2,6 +2,7 @@ config CPU_AMD_AGESA_FAMILY15_TN bool + select IDS_OPTIONS_HOOKED_UP select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index ce59fe1..2b89418 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -1,5 +1,61 @@ # SPDX-License-Identifier: GPL-2.0-only +config IDS_OPTIONS_HOOKED_UP + bool + help + to Kconfig options. + Historically, IDS configuration was defined in a mainboard-specific + `OptionsIds.h` header. Select this on platforms where IDS config is + hooked up to Kconfig options instead. + +if IDS_OPTIONS_HOOKED_UP + +config IDS_ENABLED + bool "Enable AGESA IDS (Integrated Debug Services) support" + default y + help + This is the master switch for the IDS sub-system. Use this option to + enable or remove the entire IDS feature set. This switch must be TRUE + for any of the other options to function. + +comment "Warning: IDS options may not work. Enable at your own risk!" + depends on IDS_ENABLED + +config IDS_CONTROL_ENABLED + bool "Enable IDS User Interface controls" + depends on IDS_ENABLED + help + This is the main switch for the IDS configuration controls. This + switch must be TRUE for any of the configuration controls to function. + + This seems to allow AGESA to retrieve settings from CMOS. + +config IDS_PERF_ANALYSIS + bool "Enable IDS performance analysis" + depends on IDS_ENABLED + help + This is the main switch for the IDS performance analysis controls, + macros and support code needed to enable time data gathering. This + switch must be TRUE for any of the performance analysis features to + function. + +config IDS_TRACING_ENABLED + bool "Enable IDS console" + depends on IDS_ENABLED + help + This is the main switch for the IDS console controls, macros and + support code needed to enable tracing of algorithms. This switch + must be TRUE for any of the tracing features to function. + +config IDS_TRACING_CONSOLE_SERIAL + bool "Use serial port as IDS console" + depends on IDS_TRACING_ENABLED + default DRIVERS_UART_8250IO && CONSOLE_SERIAL + help + Use an I/O-mapped serial port to output IDS messages. + +endif # IDS_OPTIONS_HOOKED_UP + choice prompt "DDR3 memory profile" default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC diff --git a/src/vendorcode/amd/agesa/f15tn/OptionsIds.h b/src/vendorcode/amd/agesa/f15tn/OptionsIds.h index 77b239d..cf16de3 100644 --- a/src/vendorcode/amd/agesa/f15tn/OptionsIds.h +++ b/src/vendorcode/amd/agesa/f15tn/OptionsIds.h @@ -1,33 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - */ #ifndef _OPTION_IDS_H_ #define _OPTION_IDS_H_ -/** - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_IDS_ENABLED CONFIG(IDS_ENABLED) +#define IDSOPT_CONTROL_ENABLED CONFIG(IDS_CONTROL_ENABLED) +#define IDSOPT_PERF_ANALYSIS CONFIG(IDS_PERF_ANALYSIS) +#define IDSOPT_TRACING_ENABLED CONFIG(IDS_TRACING_ENABLED) +#define IDSOPT_TRACING_CONSOLE_SERIALPORT CONFIG(IDS_TRACING_CONSOLE_SERIAL) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/53985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6 Gerrit-Change-Number: 53985 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: AGESA f15tn: Hook up IDS options to Kconfig
by David Hendricks (Code Review) 23 Aug '21

23 Aug '21

Attention is currently required from: Mike Banon, Michał Żygowski, Angel Pons, Arthur Heymans, Kyösti Mälkki, Felix Held. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53985 ) Change subject: AGESA f15tn: Hook up IDS options to Kconfig ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6 Gerrit-Change-Number: 53985 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 22 Aug 2021 22:16:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: AGESA f15tn: Factor out common OptionsIds.h
by David Hendricks (Code Review) 23 Aug '21

23 Aug '21

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53984 ) Change subject: AGESA f15tn: Factor out common OptionsIds.h ...................................................................... AGESA f15tn: Factor out common OptionsIds.h Subsequent commits will add Kconfig options to configure IDS. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: I861762280b274566ce14969a30e2e0c98e120a69 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- D src/mainboard/amd/parmer/OptionsIds.h D src/mainboard/amd/thatcher/OptionsIds.h D src/mainboard/asus/f2a85-m/OptionsIds.h D src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h D src/mainboard/lenovo/g505s/OptionsIds.h D src/mainboard/msi/ms7721/OptionsIds.h M src/vendorcode/amd/agesa/f15tn/Makefile.inc R src/vendorcode/amd/agesa/f15tn/OptionsIds.h 8 files changed, 0 insertions(+), 217 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h deleted file mode 100644 index d109d2f..0000000 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE - -#endif diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h deleted file mode 100644 index d109d2f..0000000 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE - -#endif diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h deleted file mode 100644 index d109d2f..0000000 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE - -#endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h deleted file mode 100644 index d109d2f..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE - -#endif diff --git a/src/mainboard/lenovo/g505s/OptionsIds.h b/src/mainboard/lenovo/g505s/OptionsIds.h deleted file mode 100644 index d109d2f..0000000 --- a/src/mainboard/lenovo/g505s/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE - -#endif diff --git a/src/mainboard/msi/ms7721/OptionsIds.h b/src/mainboard/msi/ms7721/OptionsIds.h deleted file mode 100644 index d109d2f..0000000 --- a/src/mainboard/msi/ms7721/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE - -#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 674ec60..6769ecb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -33,7 +33,6 @@ AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/../common AGESA_INC += -I$(AGESA_ROOT)/Include -AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/vendorcode/amd/agesa/f15tn/OptionsIds.h similarity index 100% rename from src/mainboard/asus/a88xm-e/OptionsIds.h rename to src/vendorcode/amd/agesa/f15tn/OptionsIds.h -- To view, visit https://review.coreboot.org/c/coreboot/+/53984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I861762280b274566ce14969a30e2e0c98e120a69 Gerrit-Change-Number: 53984 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`
by David Hendricks (Code Review) 23 Aug '21

23 Aug '21

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53983 ) Change subject: AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED` ...................................................................... AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED` The `ASSERT` macro is already defined in `src/include/assert.h`, and AGESA's definition is never used. On Asus A88XM-E, toggling the value of the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary when using reproducible builds. Attempting to use AGESA's definition of the `ASSERT` macro results in build errors: In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info': src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value] #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); Given that coreboot's definition of `ASSERT` is more useful, drop AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro. Also remove the `IdsAssert` function, as it is no longer used anywhere. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/amd/parmer/OptionsIds.h M src/mainboard/amd/thatcher/OptionsIds.h M src/mainboard/asus/a88xm-e/OptionsIds.h M src/mainboard/asus/f2a85-m/OptionsIds.h M src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h M src/mainboard/lenovo/g505s/OptionsIds.h M src/mainboard/msi/ms7721/OptionsIds.h M src/vendorcode/amd/agesa/f15tn/Include/Ids.h M src/vendorcode/amd/agesa/f15tn/MainPage.h M src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c 10 files changed, 0 insertions(+), 94 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h index 130d852..d109d2f 100644 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ b/src/mainboard/amd/parmer/OptionsIds.h @@ -23,7 +23,6 @@ * IDSOPT_CONTROL_ENABLED * IDSOPT_TRACING_ENABLED * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED * **/ @@ -33,6 +32,5 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE //#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE #endif diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h index 130d852..d109d2f 100644 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -23,7 +23,6 @@ * IDSOPT_CONTROL_ENABLED * IDSOPT_TRACING_ENABLED * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED * **/ @@ -33,6 +32,5 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE //#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE #endif diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h index 33b0232..77b239d 100644 --- a/src/mainboard/asus/a88xm-e/OptionsIds.h +++ b/src/mainboard/asus/a88xm-e/OptionsIds.h @@ -21,7 +21,6 @@ * IDSOPT_CONTROL_ENABLED * IDSOPT_TRACING_ENABLED * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED **/ @@ -30,6 +29,5 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE //#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE #endif diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h index 130d852..d109d2f 100644 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ b/src/mainboard/asus/f2a85-m/OptionsIds.h @@ -23,7 +23,6 @@ * IDSOPT_CONTROL_ENABLED * IDSOPT_TRACING_ENABLED * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED * **/ @@ -33,6 +32,5 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE //#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE #endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h index 130d852..d109d2f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h @@ -23,7 +23,6 @@ * IDSOPT_CONTROL_ENABLED * IDSOPT_TRACING_ENABLED * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED * **/ @@ -33,6 +32,5 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE //#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE #endif diff --git a/src/mainboard/lenovo/g505s/OptionsIds.h b/src/mainboard/lenovo/g505s/OptionsIds.h index 130d852..d109d2f 100644 --- a/src/mainboard/lenovo/g505s/OptionsIds.h +++ b/src/mainboard/lenovo/g505s/OptionsIds.h @@ -23,7 +23,6 @@ * IDSOPT_CONTROL_ENABLED * IDSOPT_TRACING_ENABLED * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED * **/ @@ -33,6 +32,5 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE //#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE #endif diff --git a/src/mainboard/msi/ms7721/OptionsIds.h b/src/mainboard/msi/ms7721/OptionsIds.h index 130d852..d109d2f 100644 --- a/src/mainboard/msi/ms7721/OptionsIds.h +++ b/src/mainboard/msi/ms7721/OptionsIds.h @@ -23,7 +23,6 @@ * IDSOPT_CONTROL_ENABLED * IDSOPT_TRACING_ENABLED * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED * **/ @@ -33,6 +32,5 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE //#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE #endif diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h index 95d726d..09a2341 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h @@ -223,10 +223,6 @@ #define IDSOPT_HEAP_CHECKING FALSE #endif -#ifndef IDSOPT_ASSERT_ENABLED - #define IDSOPT_ASSERT_ENABLED FALSE -#endif - #ifndef IDSOPT_ERROR_TRAP_ENABLED #define IDSOPT_ERROR_TRAP_ENABLED FALSE #endif @@ -264,7 +260,6 @@ #undef IDSOPT_TRACING_ENABLED #undef IDSOPT_PERF_ANALYSIS #undef IDSOPT_HEAP_CHECKING - #undef IDSOPT_ASSERT_ENABLED #undef IDSOPT_ERROR_TRAP_ENABLED #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED #undef IDSOPT_DEBUG_CODE_ENABLED @@ -277,7 +272,6 @@ #define IDSOPT_TRACING_ENABLED FALSE #define IDSOPT_PERF_ANALYSIS FALSE #define IDSOPT_HEAP_CHECKING FALSE - #define IDSOPT_ASSERT_ENABLED FALSE #define IDSOPT_ERROR_TRAP_ENABLED FALSE #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE #define IDSOPT_DEBUG_CODE_ENABLED FALSE @@ -345,34 +339,6 @@ #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds." #endif -/** - * @def ASSERT - * Test an assertion that the given statement is True. - * - * The statement is evaluated to a boolean value. If the statement is True, - * then no action is taken (no error). If the statement is False, a error stop - * is generated to halt the program. Used for testing for fatal errors that - * must be resolved before production. This is used to do parameter checks, - * bounds checking, range checks and 'sanity' checks. - * - * @param[in] conditional Assert that evaluating this conditional results in TRUE. - * - **/ -#ifndef ASSERT - #if IDSOPT_ASSERT_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); - #else - #define ASSERT(conditional) - #endif -#endif - #if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE #undef IDSOPT_ERROR_TRAP_ENABLED #define IDSOPT_ERROR_TRAP_ENABLED TRUE @@ -1251,23 +1217,6 @@ ); /** - * IDS Backend Function for ASSERT - * - * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that - * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display, - * to help distinguish the stop code from a post code loop. - * Additional features may be available if using simulation. - * - * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num. - * - * @retval TRUE No error -**/ -BOOLEAN -IdsAssert ( - IN UINT32 FileCode - ); - -/** * The engine code for ASSERT MACRO * * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that diff --git a/src/vendorcode/amd/agesa/f15tn/MainPage.h b/src/vendorcode/amd/agesa/f15tn/MainPage.h index 503aa4a..52094c5 100644 --- a/src/vendorcode/amd/agesa/f15tn/MainPage.h +++ b/src/vendorcode/amd/agesa/f15tn/MainPage.h @@ -90,7 +90,6 @@ * @code * #define IDSOPT_IDS_ENABLED TRUE * #define IDSOPT_ERROR_TRAP_ENABLED TRUE - * #define IDSOPT_ASSERT_ENABLED TRUE * @endcode * <li> Edit and modify the option selections in those two files to meet the needs of the specific platform. * <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code. diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c index b5c26ae..45b25a4 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c @@ -78,34 +78,6 @@ } /** - * IDS Backend Function for ASSERT - * - * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that - * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display, - * to help distinguish the stop code from a post code loop. - * Additional features may be available if using simulation. - * - * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num. - * - * @retval TRUE No error - **/ -BOOLEAN -IdsAssert ( - IN UINT32 FileCode - ) -{ - UINT32 file; - UINT32 line; - - file = (FileCode >> 16); - line = (FileCode & 0xFFFF); - IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%x] Line[%x]\n", (UINTN) file, (UINTN) line); - IDS_HDT_CONSOLE_FLUSH_BUFFER (NULL); - IDS_HDT_CONSOLE_ASSERT (FileCode); - return TRUE; -} - -/** * IDS Backend Function for Memory timeout control * * This function is used to override Memory timeout control. -- To view, visit https://review.coreboot.org/c/coreboot/+/53983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Gerrit-Change-Number: 53983 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit August 2021