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Change subject: drivers/gfx/nvidia: Add driver for NVIDIA Optimus
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57034/comment/1085a59c_af3cfbee
PS2, Line 12:
> Thanks for pointer Michael! I think there would be two set of requirements: […]
I didn't look too closely, but looks like the PM enter/exit sequences only touch root port configuration registers (dGPU registers are not accessed). SA PEG and PCH PCIe root ports have different magic sequences, but the rough idea is the same.
I might have mixed up the order (the reference ASL is horrible), but it's roughly something like this:
Power down: PCIe root port config is saved, then the PCIe link is brought down (and PEG bundles are disabled), then the dGPU reset signal is asserted, and finally the dGPU is power gated.
Power up: dGPU power is enabled, then dGPU is taken out of reset, then the PCIe link is brought up (PEG bundles also need to be re-enabled), and finally PCIe root port config is restored.
The dGPU power and reset control is usually done using two GPIOs, which is mainboard-specific. The PCIe root port code is SoC-specific (but I think it doesn't change much).
This is why I suggested using a runtime-generated SSDT. The PCIe root port magic for SA PEG and PCH PCIe can be defined as ACPI methods in SoC code (either in the DSDT or a SSDT). The generated Optimus SSDT would then have calls to the methods of the devicetree-specified root port. The ACPI code handling the dGPU GPIOs could also be runtime-generated (provided that the devicetree contains GPIO info).
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Change subject: mb/google/octopus: add CBI SKU RAM ID 5
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56982/comment/1a9cbfa9_a9a4ceeb
PS2, Line 13: NONE
Octopus
https://review.coreboot.org/c/coreboot/+/56982/comment/0fd9604b_dc458908
PS2, Line 14: TEST
What is the DRAM ID used in this TEST?
File src/mainboard/google/octopus/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/56982/comment/1649a69c_64c7a852
PS2, Line 168: Dual Channel
Dual Channel / Dual Rank
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Change subject: mb/google/dedede/var/sasukette: Add FW_CONFIG probe for EXT_VR
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Patch Set 15:
(1 comment)
Patchset:
PS15:
FW_CONFIG 18 has been added in Dedede program.star.
Please help to review code, thanks.
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Change subject: acpi: Fill fadt->century based on Kconfig
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56218/comment/56c3296f_4b9607bd
PS1, Line 7: acpi: Fill fadt->century based on Kconfig
> Only in combination with the usual option tables. If the FADT entry […]
Ack
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Change subject: [RFC] PCI: Introduce `enable_mmconf()` function
......................................................................
Patch Set 1:
(1 comment)
File src/lib/bootblock.c:
https://review.coreboot.org/c/coreboot/+/57046/comment/04ae4009_e7ea5970
PS1, Line 45: if (CONFIG(MMCONF_SUPPORT))
: enable_mmconf();
> For AMD, the configuration registers is per-core MSR so the call cannot be removed from the non-BSP […]
Yes, I saw. AMD platforms could have another call to this function in AP codepath.
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Change subject: Revert "soc/intel/broadwell/pch: Drop device NVS remainders"
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Patchset:
PS4:
I really hate the current dependency on hardcoded NVS offsets, but I have no means to test any possible alternative.
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