coreboot-gerrit July 2021

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Change in coreboot[master]: src/soc/intel/*: Change legacy_8254_timer to CMOS option
by Angel Pons (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56256 ) Change subject: src/soc/intel/*: Change legacy_8254_timer to CMOS option ...................................................................... Patch Set 4: Code-Review-1 (3 comments) Patchset: PS4: Please don't make this setting *only* configurable via CMOS. Making this setting configurable using either Kconfig or CMOS is possible and simpler to implement (see comment in soc/intel/skylake code). File src/mainboard/hp/280_g2/cmos.default: https://review.coreboot.org/c/coreboot/+/56256/comment/ed5d580b_fa21bfd9 PS4, Line 1: legacy_8254_timer=Disable Why `Disable`? The default for this board is to enable 8254. Moreover, this file and cmos.layout are dead: one can't use them if HAVE_CMOS_DEFAULT and HAVE_OPTION_TABLE are not selected. I'm against making this option *only* configurable via CMOS. I've suggested an approach in a comment on soc/intel/skylake code that does not require touching any mainboards. File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/56256/comment/444c9f53_c96d6561 PS4, Line 346: 1 If you leave the Kconfig option as-is and use `CONFIG(USE_LEGACY_8254_TIMER)` as the argument for `fallback`, you don't need to touch any mainboards. const bool legacy_8254_timer = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); -- To view, visit https://review.coreboot.org/c/coreboot/+/56256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Gerrit-Change-Number: 56256 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 13:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/*: Change legacy_8254_timer to CMOS option
by Sean Rhodes (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Jeremy Soller, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56256 to look at the new patch set (#3). Change subject: src/soc/intel/*: Change legacy_8254_timer to CMOS option ...................................................................... src/soc/intel/*: Change legacy_8254_timer to CMOS option Change legacy_8254_timer to be CMOS option rather than Kconfig to allow it to be changed at runtime. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 --- M src/mainboard/hp/280_g2/Kconfig A src/mainboard/hp/280_g2/cmos.default A src/mainboard/hp/280_g2/cmos.layout M src/mainboard/purism/librem_cnl/Kconfig A src/mainboard/purism/librem_cnl/cmos.default A src/mainboard/purism/librem_cnl/cmos.layout M src/mainboard/system76/lemp9/Kconfig A src/mainboard/system76/lemp9/cmos.default A src/mainboard/system76/lemp9/cmos.layout M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/timer/Kconfig M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 17 files changed, 130 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/56256/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Gerrit-Change-Number: 56256 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/soc/intel/*: Change legacy_8254_timer to CMOS option
by build bot (Jenkins) (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56256 ) Change subject: src/soc/intel/*: Change legacy_8254_timer to CMOS option ...................................................................... Patch Set 2: (3 comments) File src/soc/intel/cannonlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123945): https://review.coreboot.org/c/coreboot/+/56256/comment/a7f66cda_091b2ca1 PS2, Line 431: params->Enable8254ClockGating = !legacy_8254_timer;; Statements terminations use 1 semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123945): https://review.coreboot.org/c/coreboot/+/56256/comment/8875a14b_821aaab4 PS2, Line 432: params->Enable8254ClockGatingOnS3 = !legacy_8254_timer;; Statements terminations use 1 semicolon File src/soc/intel/jasperlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123945): https://review.coreboot.org/c/coreboot/+/56256/comment/55432b4c_e40e9e6e PS2, Line 91: params->Enable8254ClockGating = !legacy_8254_timer;; Statements terminations use 1 semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/56256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Gerrit-Change-Number: 56256 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 12:46:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT
by Michael Niewöhner (Code Review) 13 Jul '21

13 Jul '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56198 ) Change subject: mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT ...................................................................... mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown. Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index ccbe804..52d8f1c 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -8,6 +8,10 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 4416dbf..37a33e7 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -8,6 +8,10 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/56198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5 Gerrit-Change-Number: 56198 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT
by Michael Niewöhner (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Felix Singer. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56198 ) Change subject: mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5 Gerrit-Change-Number: 56198 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Tue, 13 Jul 2021 12:42:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/*: Change legacy_8254_timer to CMOS option
by build bot (Jenkins) (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56256 ) Change subject: src/soc/intel/*: Change legacy_8254_timer to CMOS option ...................................................................... Patch Set 2: (3 comments) File src/soc/intel/cannonlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123944): https://review.coreboot.org/c/coreboot/+/56256/comment/ab838cb4_4ba251ba PS2, Line 431: params->Enable8254ClockGating = !legacy_8254_timer;; Statements terminations use 1 semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123944): https://review.coreboot.org/c/coreboot/+/56256/comment/851bd0db_653594a7 PS2, Line 432: params->Enable8254ClockGatingOnS3 = !legacy_8254_timer;; Statements terminations use 1 semicolon File src/soc/intel/jasperlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123944): https://review.coreboot.org/c/coreboot/+/56256/comment/3525efd5_aa843f68 PS2, Line 91: params->Enable8254ClockGating = !legacy_8254_timer;; Statements terminations use 1 semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/56256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Gerrit-Change-Number: 56256 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 12:38:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/*: Change legacy_8254_timer to CMOS option
by build bot (Jenkins) (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jeremy Soller, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56256 ) Change subject: src/soc/intel/*: Change legacy_8254_timer to CMOS option ...................................................................... Patch Set 1: (3 comments) File src/soc/intel/cannonlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123943): https://review.coreboot.org/c/coreboot/+/56256/comment/fab48083_b853557c PS1, Line 431: params->Enable8254ClockGating = !legacy_8254_timer;; Statements terminations use 1 semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123943): https://review.coreboot.org/c/coreboot/+/56256/comment/2f3ac838_0caac21c PS1, Line 432: params->Enable8254ClockGatingOnS3 = !legacy_8254_timer;; Statements terminations use 1 semicolon File src/soc/intel/jasperlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123943): https://review.coreboot.org/c/coreboot/+/56256/comment/8c824125_8cf306ea PS1, Line 91: params->Enable8254ClockGating = !legacy_8254_timer;; Statements terminations use 1 semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/56256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Gerrit-Change-Number: 56256 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 12:38:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/*: Change legacy_8254_timer to CMOS option
by Sean Rhodes (Code Review) 13 Jul '21

13 Jul '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56256 ) Change subject: src/soc/intel/*: Change legacy_8254_timer to CMOS option ...................................................................... src/soc/intel/*: Change legacy_8254_timer to CMOS option Change legacy_8254_timer to be CMOS option rather than Kconfig to allow it to be changed at runtime. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 --- M src/mainboard/hp/280_g2/Kconfig A src/mainboard/hp/280_g2/cmos.default A src/mainboard/hp/280_g2/cmos.layout M src/mainboard/purism/librem_cnl/Kconfig A src/mainboard/purism/librem_cnl/cmos.default A src/mainboard/purism/librem_cnl/cmos.layout M src/mainboard/system76/lemp9/Kconfig A src/mainboard/system76/lemp9/cmos.default A src/mainboard/system76/lemp9/cmos.layout M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/timer/Kconfig M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 17 files changed, 130 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/56256/1 diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig index 10f6828..8102d66 100644 --- a/src/mainboard/hp/280_g2/Kconfig +++ b/src/mainboard/hp/280_g2/Kconfig @@ -36,7 +36,4 @@ int default 2 -config USE_LEGACY_8254_TIMER - default y - endif diff --git a/src/mainboard/hp/280_g2/cmos.default b/src/mainboard/hp/280_g2/cmos.default new file mode 100644 index 0000000..cde52aa --- /dev/null +++ b/src/mainboard/hp/280_g2/cmos.default @@ -0,0 +1 @@ +legacy_8254_timer=Disable diff --git a/src/mainboard/hp/280_g2/cmos.layout b/src/mainboard/hp/280_g2/cmos.layout new file mode 100644 index 0000000..3012f30 --- /dev/null +++ b/src/mainboard/hp/280_g2/cmos.layout @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: Devices +453 1 e 1 legacy_8254_timer + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +# ----------------------------------------------------------------- +checksums + +checksum 392 453 984 diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 5763a19..8723bee 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -11,7 +11,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_CACHE_IN_FMAP select SPD_READ_BY_WORD - select USE_LEGACY_8254_TIMER if BOARD_PURISM_BASEBOARD_LIBREM_CNL diff --git a/src/mainboard/purism/librem_cnl/cmos.default b/src/mainboard/purism/librem_cnl/cmos.default new file mode 100644 index 0000000..cde52aa --- /dev/null +++ b/src/mainboard/purism/librem_cnl/cmos.default @@ -0,0 +1 @@ +legacy_8254_timer=Disable diff --git a/src/mainboard/purism/librem_cnl/cmos.layout b/src/mainboard/purism/librem_cnl/cmos.layout new file mode 100644 index 0000000..3012f30 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/cmos.layout @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: Devices +453 1 e 1 legacy_8254_timer + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +# ----------------------------------------------------------------- +checksums + +checksum 392 453 984 diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index 675b738..9bef81a 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -19,7 +19,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP - select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB config MAINBOARD_DIR string diff --git a/src/mainboard/system76/lemp9/cmos.default b/src/mainboard/system76/lemp9/cmos.default new file mode 100644 index 0000000..cde52aa --- /dev/null +++ b/src/mainboard/system76/lemp9/cmos.default @@ -0,0 +1 @@ +legacy_8254_timer=Disable diff --git a/src/mainboard/system76/lemp9/cmos.layout b/src/mainboard/system76/lemp9/cmos.layout new file mode 100644 index 0000000..3012f30 --- /dev/null +++ b/src/mainboard/system76/lemp9/cmos.layout @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: Devices +453 1 e 1 legacy_8254_timer + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +# ----------------------------------------------------------------- +checksums + +checksum 392 453 984 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5b0d631..a5cf6c6 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -8,6 +8,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> @@ -22,6 +23,7 @@ #include <soc/soc_chip.h> #include <stdlib.h> #include <string.h> +#include <types.h> /* THC assignment definition */ #define THC_NONE 0 @@ -489,8 +491,9 @@ const struct soc_intel_alderlake_config *config) { /* Legacy 8254 timer support */ - s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + s_cfg->Enable8254ClockGating = !legacy_8254_timer; + s_cfg->Enable8254ClockGatingOnS3 = !legacy_8254_timer; } static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 9d2d722..28ff0fc 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/power_limit.h> @@ -17,6 +18,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> +#include <types.h> #include "chip.h" @@ -425,8 +427,9 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer;; + params->Enable8254ClockGatingOnS3 = !legacy_8254_timer;; params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index 42613a8..e8d7207 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -3,16 +3,3 @@ help Intel Processor common TIMER support -config USE_LEGACY_8254_TIMER - bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN - default n - help - Setting this makes the Legacy 8254 Timer available by disabling - clock gating. This needs to be enabled in order to boot a legacy - BIOS or OS not supporting other timers like PM timer or TSC. - - While SeaBIOS does not require this timer anymore, it is needed - when OpRoms are being used. - - Disable this setting to save power, when the timer is not needed. diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 210040e..a10f6e2 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -5,6 +5,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/pmclib.h> @@ -15,6 +16,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <types.h> /* SATA DEVSLP idle timeout default values */ #define DEF_DMVAL 15 @@ -142,7 +144,8 @@ params->PavpEnable = 0; /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer; params->Enable8254ClockGatingOnS3 = 1; /* PCH Master Gating Control */ diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 2d63097..6301cc4 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -4,16 +4,18 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> +#include <intelblocks/mp_init.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> -#include <intelblocks/mp_init.h> -#include <fsp/ppi/mp_service_ppi.h> +#include <types.h> static void parse_devicetree(FSP_S_CONFIG *params) { @@ -93,8 +95,9 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer; + params->Enable8254ClockGatingOnS3 = !legacy_8254_timer; /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 45bed5e..d502ce3 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -5,6 +5,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/pmclib.h> @@ -15,6 +16,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <types.h> /* * ME End of Post configuration @@ -85,7 +87,8 @@ params->EndOfPostMessage = EOP_DISABLE; /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer;; params->Enable8254ClockGatingOnS3 = 1; /* disable Legacy PME */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 2599e12..51fcabd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -18,6 +18,7 @@ #include <intelblocks/xdci.h> #include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> +#include <option.h> #include <soc/acpi.h> #include <soc/intel/common/vbt.h> #include <soc/interrupt.h> @@ -29,6 +30,7 @@ #include <soc/systemagent.h> #include <soc/usb.h> #include <string.h> +#include <types.h> #include "chip.h" @@ -341,7 +343,8 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* Legacy 8254 timer support */ - params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Early8254ClockGatingEnable = !legacy_8254_timer; params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index afbd747..a2b8dba 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -10,6 +10,7 @@ #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <option.h> #include <intelblocks/cse.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> @@ -26,6 +27,7 @@ #include <soc/soc_chip.h> #include <soc/tcss.h> #include <string.h> +#include <types.h> /* THC assignment definition */ #define THC_NONE 0 @@ -547,8 +549,9 @@ params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); - params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + const unsigned int legacy_8254_timer = get_uint_option("legacy_8254_timer", 1); + params->Enable8254ClockGating = !legacy_8254_timer; + params->Enable8254ClockGatingOnS3 = !legacy_8254_timer; /* Enable Hybrid storage auto detection */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite() -- To view, visit https://review.coreboot.org/c/coreboot/+/56256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Gerrit-Change-Number: 56256 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: payloads: FILO: Hook up autoboot options
by Nico Huber (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Martin Roth, Paul Menzel, Stefan Reinauer. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56213 ) Change subject: payloads: FILO: Hook up autoboot options ...................................................................... Patch Set 2: (1 comment) File payloads/external/FILO/Makefile: https://review.coreboot.org/c/coreboot/+/56213/comment/d67ad0d7_3ded6d8a PS2, Line 39: echo "CONFIG_AUTOBOOT_FILE=$(CONFIG_FILO_AUTOBOOT_FILE)" >> filo/.config > Sorry for withholding more context. […] Oh it just looks the same because that's almost the default? :) Maybe missing quotes? e.g. CONFIG_AUTOBOOT_FILE="hda1:..." You can either use \" or replace the outer ones with single quotes. -- To view, visit https://review.coreboot.org/c/coreboot/+/56213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id167e9a144bf466da87469108002672b299b702a Gerrit-Change-Number: 56213 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 12:31:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads: FILO: Hook up autoboot options
by Paul Menzel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Nico Huber, Martin Roth, Stefan Reinauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56213 ) Change subject: payloads: FILO: Hook up autoboot options ...................................................................... Patch Set 2: (1 comment) File payloads/external/FILO/Makefile: https://review.coreboot.org/c/coreboot/+/56213/comment/7c37d720_bc6b484c PS2, Line 39: echo "CONFIG_AUTOBOOT_FILE=$(CONFIG_FILO_AUTOBOOT_FILE)" >> filo/.config > I don't understand. […] Sorry for withholding more context. The argument `root=` for Linux is different: `/dev/sda1` (changed in coreboot’s config) vs. `/dev/hda1`. It’s added at the top, but at the end FILO’s default is taken. -- To view, visit https://review.coreboot.org/c/coreboot/+/56213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id167e9a144bf466da87469108002672b299b702a Gerrit-Change-Number: 56213 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 12:25:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit July 2021