coreboot-gerrit July 2021

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00
by Tim Wawrzynczak (Code Review) 13 Jul '21

13 Jul '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55896 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00 ...................................................................... vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00 The headers added are generated as per FSP v2237_00. Previous FSP version was v2207_01. Changes Include: - Add VccInAuxImonIccImax in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:192199787 BRANCH=None TEST=Build and boot brya Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Cq-Depend:chrome-internal:3970327,chrome-internal:3925290 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 22 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 65c8c02..76c8fd6 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -454,9 +454,10 @@ UINT8 ApertureSize; /** Offset 0x01D0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC + DDR5, 5=ULT/ULX/Mobile Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 2:Desktop 2DPC DDR5, 5:ULT/ULX/Mobile Halo, + 7:UP Server **/ UINT8 UserBd; @@ -2939,12 +2940,12 @@ UINT8 Reserved38[3]; /** Offset 0x08DE - REFRESH_PANIC_WM - Refresh Panic Watermark, range 1-8, Default is 8 + DEPRECATED **/ UINT8 RefreshPanicWm; /** Offset 0x08DF - REFRESH_HP_WM - Refresh High Priority Watermark, range 1-7, Default is 7 + DEPRECATED **/ UINT8 RefreshHpWm; @@ -3161,7 +3162,7 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved46[56]; + UINT8 Reserved46[64]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3180,11 +3181,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0AE0 +/** Offset 0x0AE8 **/ UINT8 UnusedUpdSpace29[6]; -/** Offset 0x0AE6 +/** Offset 0x0AEE **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 7fd87892..d689bd8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1547,9 +1547,15 @@ **/ UINT16 VrVoltageLimit[5]; -/** Offset 0x069E - Reserved +/** Offset 0x069E - VccIn Aux Imon IccMax + PCODE MMIO Mailbox: VccIn Aux Imon IccMax. <b>0 - Auto</b> Values are in 1/4 Amp + increments. Range is 0-512. **/ - UINT8 Reserved27[12]; + UINT16 VccInAuxImonIccImax; + +/** Offset 0x06A0 - Reserved +**/ + UINT8 Reserved27[10]; /** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b> @@ -1960,8 +1966,8 @@ UINT8 PcieComplianceTestMode; /** Offset 0x09CA - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. + DEPRECATED. Allows BIOS to use root port function number swapping when root port + of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; @@ -3861,7 +3867,7 @@ /** Offset 0x0FD5 - Reserved **/ - UINT8 Reserved57[3]; + UINT8 Reserved57[11]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3880,11 +3886,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0FD8 +/** Offset 0x0FE0 **/ UINT8 UnusedUpdSpace40[6]; -/** Offset 0x0FDE +/** Offset 0x0FE6 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/55896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Gerrit-Change-Number: 55896 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/mca: use mca_clear_status()
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56260 ) Change subject: soc/amd/picasso/mca: use mca_clear_status() ...................................................................... soc/amd/picasso/mca: use mca_clear_status() Since we can use both the old MCA registers and the new MCAX registers to access the MCA status registers, we can use the common mca_clear_status function here. Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c 1 file changed, 3 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/56260/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 973b3b5..23d7b61 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -181,19 +181,11 @@ } } -static void mca_clear_errors(void) -{ - const unsigned int num_banks = mca_get_bank_count(); - const msr_t msr = {.lo = 0, .hi = 0}; - - /* Zero all machine check error status registers */ - for (unsigned int i = 0 ; i < num_banks ; i++) - wrmsr(MCAX_STATUS_MSR(i), msr); -} - /* Check the Machine Check Architecture Extension registers */ void check_mca(void) { mca_check_all_banks(); - mca_clear_errors(); + /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are + aliases, we can use either set of registers. */ + mca_clear_status(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26 Gerrit-Change-Number: 56260 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: use mca_clear_status function instead of open coding
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Patrick Rudolph. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56259 ) Change subject: src: use mca_clear_status function instead of open coding ...................................................................... src: use mca_clear_status function instead of open coding Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/common/block/cpu/cpulib.c 9 files changed, 11 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56259/1 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 76c8521..369ed5a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -17,7 +17,6 @@ { u8 i; msr_t msr; - unsigned int num_banks; int msrno; #if CONFIG(LOGICAL_CPUS) u32 siblings; @@ -59,11 +58,7 @@ x86_enable_cache(); /* zero the machine check error status registers */ - num_banks = mca_get_bank_count(); - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC_STATUS(i), msr); + mca_clear_status(); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 883bd59..356647a 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -20,7 +20,6 @@ u8 i; msr_t msr; - unsigned int num_banks; int msrno; unsigned int cpu_idx; #if CONFIG(LOGICAL_CPUS) @@ -58,11 +57,7 @@ x86_enable_cache(); /* zero the machine check error status registers */ - num_banks = mca_get_bank_count(); - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC_STATUS(i), msr); + mca_clear_status(); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index f945f80..f01f840 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -19,7 +19,6 @@ u8 i; msr_t msr; - unsigned int num_banks; int msrno; #if CONFIG(LOGICAL_CPUS) u32 siblings; @@ -56,11 +55,7 @@ x86_enable_cache(); /* zero the machine check error status registers */ - num_banks = mca_get_bank_count(); - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC_STATUS(i), msr); + mca_clear_status(); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 3c78c09..07836fc 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -22,7 +22,6 @@ u8 i; msr_t msr; - unsigned int num_banks; u32 siblings; /* @@ -41,11 +40,7 @@ x86_mtrr_check(); /* zero the machine check error status registers */ - num_banks = mca_get_bank_count(); - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC_STATUS(i), msr); + mca_clear_status(); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 29c663e..2c6384c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -527,12 +527,10 @@ for (i = 0; i < num_banks; i++) wrmsr(IA32_MC_CTL(i), msr); - msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC_STATUS(i), msr); + mca_clear_status(); } /* All CPUs including BSP will run the following function. */ diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index fe5ac56..f70d7b2 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -73,24 +73,13 @@ ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK); } -static void configure_mca(void) -{ - msr_t msr; - int i; - const unsigned int num_banks = mca_get_bank_count(); - - msr.lo = msr.hi = 0; - /* This should only be done on a cold boot */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC_STATUS(i), msr); -} - static void model_2065x_init(struct device *cpu) { char processor_name[49]; /* Clear out pending MCEs */ - configure_mca(); + /* This should only be done on a cold boot */ + mca_clear_status(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 541cb3b..09cad24 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -297,18 +297,6 @@ return SANDYBRIDGE_BCLK; } -static void configure_mca(void) -{ - msr_t msr; - int i; - const unsigned int num_banks = mca_get_bank_count(); - - msr.lo = msr.hi = 0; - /* This should only be done on a cold boot */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC_STATUS(i), msr); -} - static void model_206ax_report(void) { static const char *const mode[] = {"NOT ", ""}; @@ -340,7 +328,8 @@ { /* Clear out pending MCEs */ - configure_mca(); + /* This should only be done on a cold boot */ + mca_clear_status(); /* Print infos */ model_206ax_report(); diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 0773101..e0c2791 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -186,18 +186,8 @@ } } -static void mca_clear_errors(void) -{ - const unsigned int num_banks = mca_get_bank_count(); - const msr_t msr = {.lo = 0, .hi = 0}; - - /* Zero all machine check error status registers */ - for (unsigned int i = 0 ; i < num_banks ; i++) - wrmsr(IA32_MC_STATUS(i), msr); -} - void check_mca(void) { mca_check_all_banks(); - mca_clear_errors(); + mca_clear_status(); } diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index a245824..9372513 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -336,17 +336,14 @@ void mca_configure(void) { - msr_t msr; int i; const unsigned int num_banks = mca_get_bank_count(); printk(BIOS_DEBUG, "Clearing out pending MCEs\n"); - msr.lo = msr.hi = 0; + mca_clear_status(); for (i = 0; i < num_banks; i++) { - /* Clear the machine check status */ - wrmsr(IA32_MC_STATUS(i), msr); /* Initialize machine checks */ wrmsr(IA32_MC_CTL(i), (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); -- To view, visit https://review.coreboot.org/c/coreboot/+/56259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Gerrit-Change-Number: 56259 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/x86/msr: add mca_clear_status function
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56258 ) Change subject: include/cpu/x86/msr: add mca_clear_status function ...................................................................... include/cpu/x86/msr: add mca_clear_status function In multiple locations within the coreboot tree all available IA32_MC_STATUS registers are cleared, so add this to the common code to avoid duplication of code. Change-Id: I04af23c16021b0ce90f7105f7a3856bd26ffa736 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/x86/msr.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/56258/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index dd969d7..51ef2e0 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -166,6 +166,16 @@ return msr.lo & MCA_BANKS_MASK; } +/* Clear all MCA status registers */ +static inline void mca_clear_status(void) +{ + const unsigned int num_banks = mca_get_bank_count(); + const msr_t msr = {.lo = 0, .hi = 0}; + + for (unsigned int i = 0 ; i < num_banks ; i++) + wrmsr(IA32_MC_STATUS(i), msr); +} + /* Helpers for interpreting MC[i]_STATUS */ static inline int mca_valid(msr_t msr) -- To view, visit https://review.coreboot.org/c/coreboot/+/56258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04af23c16021b0ce90f7105f7a3856bd26ffa736 Gerrit-Change-Number: 56258 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Implement WA for DDR5 DIMM modules
by Tim Wawrzynczak (Code Review) 13 Jul '21

13 Jul '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50996 ) Change subject: soc/intel/alderlake: Implement WA for DDR5 DIMM modules ...................................................................... soc/intel/alderlake: Implement WA for DDR5 DIMM modules The coreboot SMBus driver requires additional changes to accomodate the DDR5 EEPROM read which has resulted in a broken code flow for boot. This CL serves as a temp WA to let FSP perform the SPD read for DDR5 and pass SPD addresses to FSP UPD array. BUG=b:180458099 TEST=Build and boot DDR5 adlrvp to OS Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50996 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/meminit.c 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 32496ce..44071db 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -217,6 +217,22 @@ mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); } +#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm)) + +static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info) +{ + for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) { + for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { + size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch]; + mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = + spd_info->smbus[ch].addr_dimm[dimm] << 1; + } + } + mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true); + mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); +} + void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { @@ -235,9 +251,20 @@ switch (mb_cfg->type) { case MEM_TYPE_DDR4: + meminit_ddr(mem_cfg, &mb_cfg->ddr_config); + dq_dqs_auto_detect = true; + break; case MEM_TYPE_DDR5: meminit_ddr(mem_cfg, &mb_cfg->ddr_config); dq_dqs_auto_detect = true; + /* + * TODO: Drop this workaround once SMBus driver in coreboot is updated to + * support DDR5 EEPROM reading. + */ + if (spd_info->topo == MEM_TOPO_DIMM_MODULE) { + ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info); + return; + } break; case MEM_TYPE_LP4X: meminit_lp4x(mem_cfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 23 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table
by Tim Wawrzynczak (Code Review) 13 Jul '21

13 Jul '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56175 ) Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ...................................................................... soc/intel/alderlake: Add (and fix) devices in IRQ table Some devices were missing from the IRQ table, and this lack of IRQ programming for the devices (although unused), was causing S0ix entry to fail. BUG=b:176858827 TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle correctly upon entry/exit from S0ix Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56175 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 51 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 6faa393..9dec31c 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -48,7 +48,8 @@ { .slot = SA_DEV_SLOT_IGD, .fns = { - ANY_PIRQ(SA_DEVFN_IGD), + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), }, }, { @@ -60,14 +61,16 @@ { .slot = SA_DEV_SLOT_IPU, .fns = { - ANY_PIRQ(SA_DEVFN_IPU), + /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, + but S0ix fails when not set to 16 (b/193434192) */ + FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A), }, }, { .slot = SA_DEV_SLOT_CPU_6, .fns = { - ANY_PIRQ(SA_DEVFN_CPU_PCIE6_0), - ANY_PIRQ(SA_DEVFN_CPU_PCIE6_2), + FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), }, }, { @@ -80,9 +83,35 @@ }, }, { + .slot = SA_DEV_SLOT_GNA, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), + }, + }, + { .slot = SA_DEV_SLOT_TCSS, .fns = { ANY_PIRQ(SA_DEVFN_TCSS_XHCI), + ANY_PIRQ(SA_DEVFN_TCSS_XDCI), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO0, + .fns = { + DIRECT_IRQ(PCH_DEVFN_I2C6), + DIRECT_IRQ(PCH_DEVFN_I2C7), + ANY_PIRQ(PCH_DEVFN_THC0), + ANY_PIRQ(PCH_DEVFN_THC1), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO6, + .fns = { + DIRECT_IRQ(PCH_DEVFN_UART3), + DIRECT_IRQ(PCH_DEVFN_UART4), + DIRECT_IRQ(PCH_DEVFN_UART5), + DIRECT_IRQ(PCH_DEVFN_UART6), }, }, { @@ -90,12 +119,23 @@ .fns = { DIRECT_IRQ(PCH_DEVFN_ISH), DIRECT_IRQ(PCH_DEVFN_GSPI2), + ANY_PIRQ(PCH_DEVFN_UFS), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO2, + .fns = { + DIRECT_IRQ(PCH_DEVFN_GSPI3), + DIRECT_IRQ(PCH_DEVFN_GSPI4), + DIRECT_IRQ(PCH_DEVFN_GSPI5), + DIRECT_IRQ(PCH_DEVFN_GSPI6), }, }, { .slot = PCH_DEV_SLOT_XHCI, .fns = { ANY_PIRQ(PCH_DEVFN_XHCI), + DIRECT_IRQ(PCH_DEVFN_USBOTG), ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), }, }, @@ -158,10 +198,14 @@ { .slot = PCH_DEV_SLOT_SIO5, .fns = { + /* UART0 shares an interrupt line with TSN0, so must use + a PIRQ */ FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), + /* UART1 shares an interrupt line with TSN1, so must use + a PIRQ */ FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), - ANY_PIRQ(PCH_DEVFN_GSPI0), - ANY_PIRQ(PCH_DEVFN_GSPI1), + DIRECT_IRQ(PCH_DEVFN_GSPI0), + DIRECT_IRQ(PCH_DEVFN_GSPI1), }, }, { @@ -170,6 +214,7 @@ ANY_PIRQ(PCH_DEVFN_HDA), ANY_PIRQ(PCH_DEVFN_SMBUS), ANY_PIRQ(PCH_DEVFN_GBE), + /* INTERRUPT_PIN is RO/0x01 */ FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), }, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/56175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Gerrit-Change-Number: 56175 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/gma: Support IGD Opregion 2.1
by Tim Wawrzynczak (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Krishna Prabhakaran, Furquan Shaikh, Maulik V Vaghela, Selma Bensaid, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52758 ) Change subject: drivers/intel/gma: Support IGD Opregion 2.1 ...................................................................... Patch Set 24: (1 comment) File src/drivers/intel/gma/opregion.c: https://review.coreboot.org/c/coreboot/+/52758/comment/2899e618_39fece64 PS14, Line 290: CONFIG(INTEL_GMA_OPREGION_2_1) > Ping May be worth a helper function? ``` static bool uses_relative_vbt_addr(header) { return (header->opver.major >= 2 && header->opver.minor >= 1) || (header->opver.major > 2); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/52758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b Gerrit-Change-Number: 52758 Gerrit-PatchSet: 24 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 14:16:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: Support IGD Opregion 2.1
by Nico Huber (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Krishna Prabhakaran, Furquan Shaikh, Maulik V Vaghela, Selma Bensaid, Subrata Banik, Meera Ravindranath, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52758 ) Change subject: drivers/intel/gma: Support IGD Opregion 2.1 ...................................................................... Patch Set 24: (1 comment) Patchset: PS24: Any progress on getting the specification released? I'm very confused that this should be OVER 2.1. Intel already mentioned that Skylake would be 3.0r0 [1], they just didn't update the VBIOS number for unknown reasons. It seems ok to set OVER to 2.1 for a new revision, but does the document really say that it is about OpRegion 2.1? Or is this a mixup with the document revision maybe that just happens to be 2.1 as well? [1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf -- To view, visit https://review.coreboot.org/c/coreboot/+/52758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b Gerrit-Change-Number: 52758 Gerrit-PatchSet: 24 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 14:04:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table
by Maulik V Vaghela (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56175 ) Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Gerrit-Change-Number: 56175 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 14:02:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow configuring log level through CBFS
by Nico Huber (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Marc Jones, Stefan Reinauer, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow configuring log level through CBFS ...................................................................... Patch Set 17: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 13:34:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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