coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/cezanne: add basic MCA support
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56262 ) Change subject: soc/amd/cezanne: add basic MCA support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b Gerrit-Change-Number: 56262 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:36:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/amd/msr: add and use MC_CTL_MASK macro
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56261 ) Change subject: include/cpu/amd/msr: add and use MC_CTL_MASK macro ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Gerrit-Change-Number: 56261 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:36:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56246 ) Change subject: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Gerrit-Change-Number: 56246 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:35:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add basic MCA support
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56262 ) Change subject: soc/amd/cezanne: add basic MCA support ...................................................................... soc/amd/cezanne: add basic MCA support Currently the MCA support for Cezanne only clears the MCA status registers. The MCA error handling and BERT table generation will be added in subsequent patches. Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/cpu.c M src/soc/amd/cezanne/include/soc/cpu.h A src/soc/amd/cezanne/mca.c 4 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/56262/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index fa38cc3..d68a6b6 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c +ramstage-y += mca.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index ddc49a9..5f0a5a1 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -59,6 +59,7 @@ static void zen_2_3_init(struct device *dev) { + check_mca(); setup_lapic(); set_cstate_io_addr(); diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h index 27647ad..ec83349 100644 --- a/src/soc/amd/cezanne/include/soc/cpu.h +++ b/src/soc/amd/cezanne/include/soc/cpu.h @@ -5,4 +5,6 @@ #define CEZANNE_A0_CPUID 0x00a50f00 +void check_mca(void); + #endif /* AMD_CEZANNE_CPU_H */ diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c new file mode 100644 index 0000000..7160256 --- /dev/null +++ b/src/soc/amd/cezanne/mca.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <soc/cpu.h> + +/* Check the Machine Check Architecture Extension registers */ +void check_mca(void) +{ + /* TODO: Implement MCAX register checking and BERT table generation. */ + + /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are + aliases, we can use either set of registers. */ + mca_clear_status(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b Gerrit-Change-Number: 56262 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/amd/msr: add and use MC_CTL_MASK macro
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56261 ) Change subject: include/cpu/amd/msr: add and use MC_CTL_MASK macro ...................................................................... include/cpu/amd/msr: add and use MC_CTL_MASK macro Add this macro to be able to conveniently access the MC_CTL_MASK register for each MCA bank. Also drop the unused definitions for MC1_CTL_MASK and MC4_CTL_MASK. Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/amd/msr.h M src/soc/amd/stoneyridge/mca.c 2 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/56261/1 diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 9edea5a..55a7841 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -19,8 +19,7 @@ #define NB_CFG_MSR 0xC001001f #define FidVidStatus 0xC0010042 #define MC0_CTL_MASK 0xC0010044 -#define MC1_CTL_MASK 0xC0010045 -#define MC4_CTL_MASK 0xC0010048 +#define MC_CTL_MASK(bank) (MC0_CTL_MASK + (bank)) #define MSR_INTPEND 0xC0010055 #define MMIO_CONF_BASE 0xC0010058 #define MMIO_RANGE_EN (1 << 0) diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 598bfb5..d9aac91 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -123,8 +123,7 @@ ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); if (!ctx) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, - MC0_CTL_MASK + mci->bank, 1); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MC_CTL_MASK(mci->bank), 1); if (!ctx) goto failed; @@ -160,7 +159,7 @@ printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); msr = rdmsr(IA32_MC_CTL(bank)); printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + bank); + msr = rdmsr(MC_CTL_MASK(bank)); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Gerrit-Change-Number: 56261 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56246 to look at the new patch set (#3). Change subject: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr ...................................................................... include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr This MSR isn't an architectural MSR, so it shouldn't be in the common x86 MSR definition header file. From family 17h on this register has moved to a different location. Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/amd/msr.h M src/include/cpu/x86/msr.h M src/soc/amd/stoneyridge/mca.c 3 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/56246/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Gerrit-Change-Number: 56246 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Martin Roth (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/f8dd8008_dbbdba35 PS2, Line 13: however, some FSP 2.0 variants have it as well. > Re: less desirable approach. […] The FSP header has a length field. If the length is actually specified as a fixed length by the header version, this field is redundant. My opinion is that the header fields are defined by the header version, however the length is not - it's specified by the length field. I don't think we should have the header length hardcoded, and should instead rely on that length field (to a reasonable value), even if it's longer than the structure we're using. Just treat anything past the end of the structure as reserved. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Mariusz Szafrański (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Angel Pons, Michal Motyl. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Suresh Bellampalli, Subrata Banik, Angel Pons, Michal Motyl, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51180 to look at the new patch set (#3). Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... util/sconfig: Fix for multidomain support sconfig/devicetree.cb Fixes sconfig related build errors while there exists DEV.FUNC number shared by two devices from different domains (root buses) i.e. device domain 0 on device pci 00.0 on end ....... end device domain 1 on device pci 00.0 on end ....... end Two domains (each with it`s own root PCI bus) and device with 00.0 exists on both buses. Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> --- M util/sconfig/main.c 1 file changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/51180/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 3 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVP
by Sathya Prakash M R (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Sugnan Prabhu S, Subrata Banik. Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56208 ) Change subject: mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVP ...................................................................... Patch Set 2: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56208/comment/8e7e9ea5_9cdcf36d PS1, Line 7: mb/intel/adlrvp: Fix Tmode setting for ADL P RVP > Please be more specific and rephrase to something like: […] DONE https://review.coreboot.org/c/coreboot/+/56208/comment/1f5a4ed4_f0345baf PS1, Line 8: > Please describe the problem first: […] Done https://review.coreboot.org/c/coreboot/+/56208/comment/bc4ac5a7_7bfbaedd PS1, Line 13: Earlier setting was with older FSP which was carry forwarded. > What FSP version did you test with? Done https://review.coreboot.org/c/coreboot/+/56208/comment/7d650955_84c915b7 PS1, Line 13: carry > carried Done https://review.coreboot.org/c/coreboot/+/56208/comment/c3eb03dc_89beb858 PS1, Line 16: HDMI /DP > HDMI/DP Done https://review.coreboot.org/c/coreboot/+/56208/comment/b759bd2c_48794ed8 PS1, Line 17: > Please add a fixes tag: […] Sorry, not exactly clear on this ? there is no external bug on this - so what should be added under Fixes: ? -- To view, visit https://review.coreboot.org/c/coreboot/+/56208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33 Gerrit-Change-Number: 56208 Gerrit-PatchSet: 2 Gerrit-Owner: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:27:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Nikolai Vyssotski (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Marshall Dawson, Subrata Banik, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Marshall Dawson, Subrata Banik, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56190 to look at the new patch set (#3). Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... src/drivers/intel/fsp2_0: allow larger FSP 2.0 header This is in preparation for migrating EDK2 to more recent version(s). In EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0 header (FspMultiPhaseSiInitEntryOffset). This increases the length of the header from 0x48 to 0x4c. This field is not used in coreboot yet. Allow headers of both lengths to be accepted. BUG=b:180186886 TEST=build/boot with both header flavors Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 --- M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/util.c 2 files changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/56190/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021