coreboot-gerrit July 2021

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Change in coreboot[master]: thread: Add mutex
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Julius Werner, Eric Peers, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56230 ) Change subject: thread: Add mutex ...................................................................... Patch Set 3: (1 comment) File src/lib/thread.c: https://review.coreboot.org/c/coreboot/+/56230/comment/ff0bd480_1c97b72f PS2, Line 406: thread_yield_microseconds(10); > do we need an eventual timeout here to catch improper unlocks? I had that thought, but wanted to avoid adding a return value to this method. -- To view, visit https://review.coreboot.org/c/coreboot/+/56230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff Gerrit-Change-Number: 56230 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 17:11:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Peers <epeers(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: thread: Add thread_handle
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Julius Werner, Eric Peers, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56229 ) Change subject: thread: Add thread_handle ...................................................................... Patch Set 3: (1 comment) File src/include/thread.h: https://review.coreboot.org/c/coreboot/+/56229/comment/81524dc5_ba6b6b9d PS2, Line 63: /* Wait's until the thread has terminated and returns the error code */ > nit: waits Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Gerrit-Change-Number: 56229 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 17:11:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Peers <epeers(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: thread: Add thread_handle
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Julius Werner, Eric Peers, Felix Held. Hello build bot (Jenkins), Julius Werner, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56229 to look at the new patch set (#3). Change subject: thread: Add thread_handle ...................................................................... thread: Add thread_handle The thread_handle can be used to wait for a thread to exit. I also added a return value to the thread function that will be stored on the handle after it completes. This makes it easy for the callers to check if the thread completed successfully or had an error. The wait_for_thread method uses the handle to block until the thread completes. BUG=b:179699789 TEST=See thread_handle state update and see error code set correctly. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff --- M src/include/thread.h M src/lib/thread.c 2 files changed, 87 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/56229/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Gerrit-Change-Number: 56229 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 ) Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... Patch Set 3: (3 comments) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/56228/comment/d73985a7_6ac0843e PS2, Line 69: if (!IS_ALIGNED((uintptr_t)target, LPC_ROM_DMA_MIN_ALIGNMENT)) > given your comments about architectural constraints (RN, CZN+), do we need a check for that as well? I wanted to avoid specifically checking for the SoC. Otherwise we will need to update the logic for every generation. https://review.coreboot.org/c/coreboot/+/56228/comment/80142e46_3dc51ef6 PS2, Line 119: if (spi_dma_has_error()) > does this need to move above the busy check? I don't think so. If we encounter an error, the DMA controller is no longer busy. https://review.coreboot.org/c/coreboot/+/56228/comment/05ccedf2_5eb771ec PS2, Line 158: udelay(10); > why 10? will different spi speeds yield a different number here? It was just an arbitrary number. Doing very rough some math: 250 bytes / 10us @ 100 MHz (2-2-1) 166.65 bytes / 10us @ 66.6 MHz (2-2-1) 83.325 bytes / 10us @ 33.33 MHz (2-2-1) The min block size is 64 bytes. From what I've seen we normally do 1k - 64k transactions, so I think 10us should be fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 17:11:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Peers <epeers(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56228 to look at the new patch set (#3). Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality This change will make it so the standard rdev readat call will use the SPI DMA controller if the alignment is correct, and the transfer size is larger than 64 bytes. There is a magic bit that needs to be set for the SPI DMA controller to function correctly. This is only available in RN/CZN+. BUG=b:179699789 TEST=Boot guybrush to OS. This reduces loading verstage by 40ms, verifying RW by 500us and loading romstage by 500 us. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/spi_dma.c 2 files changed, 171 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56228/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Move APOB update into ramstage
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56227 ) Change subject: soc/amd/cezanne: Move APOB update into ramstage ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56227/comment/77d000c6_28043475 PS2, Line 10: it into ramstage allow us to use threads to pre-load the apob from SPI. > I thought we were storing the APOB to SPI in coreboot, where PSP is loading the APOB from SPI. […] This CL doesn't provide any boot time savings. I updated the commit message. I think the PSP reads the APOB into RAM, and then performs the memory training. If the training data has changed in RAM, coreboot then needs to write it to SPI. I'm not sure if it's enough to just compare the headers though... https://review.coreboot.org/c/coreboot/+/56227/comment/597b5df5_3b35c4e6 PS2, Line 13: and picasso > Nit the Nit: Trembyle (or equiv) and Guybrush. Done File src/soc/amd/common/block/apob/apob_cache.c: https://review.coreboot.org/c/coreboot/+/56227/comment/e250616b_377f6033 PS2, Line 187: OOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL); > If there is a reason why not before this boot state and why not after this boot state, can you pleas […] I added the comment in the CL that adds the async read. -- To view, visit https://review.coreboot.org/c/coreboot/+/56227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Gerrit-Change-Number: 56227 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 17:11:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Peers <epeers(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Move APOB update into ramstage
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56227 to look at the new patch set (#3). Change subject: soc/amd/cezanne: Move APOB update into ramstage ...................................................................... soc/amd/cezanne: Move APOB update into ramstage There is no technical reason this needs to be done in romstage. Moving it into ramstage allow us (in future CLs) to use threads to pre-load the apob from SPI. BUG=b:179699789 TEST=Boot and Ezkinil and Guybrush and verify APOB update still work Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/apob/Makefile.inc M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/include/amdblocks/apob_cache.h M src/soc/amd/picasso/romstage.c 5 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/56227/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Gerrit-Change-Number: 56227 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/usb/acpi: Avoid dereferencing maybe-NULL pointer
by Angel Pons (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. Hello Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56266 to review the following change. Change subject: drivers/usb/acpi: Avoid dereferencing maybe-NULL pointer ...................................................................... drivers/usb/acpi: Avoid dereferencing maybe-NULL pointer Do not dereference a pointer before checking whether it is NULL. Change-Id: Icbe9ae99d91fd587d8e56cf3a0dcb59834ee6d07 Found-by: Coverity CID 1458232 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/usb/acpi/usb_acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/56266/1 diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 8ada939..18175be 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -125,12 +125,12 @@ bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld) { - struct drivers_usb_acpi_config *config = usb_device->chip_info; - if (!usb_device || !usb_device->chip_info || usb_device->chip_ops != &drivers_usb_acpi_ops) return false; + struct drivers_usb_acpi_config *config = usb_device->chip_info; + if (config->use_custom_pld) *pld = config->custom_pld; else -- To view, visit https://review.coreboot.org/c/coreboot/+/56266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbe9ae99d91fd587d8e56cf3a0dcb59834ee6d07 Gerrit-Change-Number: 56266 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/usb/acpi: Replace unneeded `memcpy` use
by Angel Pons (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. Hello Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56265 to review the following change. Change subject: drivers/usb/acpi: Replace unneeded `memcpy` use ...................................................................... drivers/usb/acpi: Replace unneeded `memcpy` use A regular assignment works just as well and also allows type-checking. It also avoids a common mistake where `sizeof` is applied to a pointer to obtain the size of the data it points to, without dereferencing it. Found-by: Coverity CID 1458231 Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/usb/acpi/usb_acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/56265/1 diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index a0dadff..8ada939 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -132,7 +132,7 @@ return false; if (config->use_custom_pld) - memcpy(pld, &config->custom_pld, sizeof(pld)); + *pld = config->custom_pld; else acpi_pld_fill_usb(pld, config->type, &config->group); -- To view, visit https://review.coreboot.org/c/coreboot/+/56265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2 Gerrit-Change-Number: 56265 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/usb/acpi: Fix usb_acpi_get_pld
by Tim Wawrzynczak (Code Review) 13 Jul '21

13 Jul '21

Tim Wawrzynczak has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/56264 ) Change subject: drivers/usb/acpi: Fix usb_acpi_get_pld ...................................................................... drivers/usb/acpi: Fix usb_acpi_get_pld Commit 8e885a57b13a2 introduced a new function and Coverity found 2 bugs in it: 1) Use before NULL check 2) Incorrect size passed to memcpy() Found-by: Coverity CID 1458231 Found-by: Coverity CID 1458232 Change-Id: I424ae185f544c13c0638ff57c097d784265f2848 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/usb/acpi/usb_acpi.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/56264/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424ae185f544c13c0638ff57c097d784265f2848 Gerrit-Change-Number: 56264 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021