coreboot-gerrit July 2021

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Change in coreboot[master]: drivers/usb/acpi: Fix usb_acpi_get_pld
by Tim Wawrzynczak (Code Review) 13 Jul '21

13 Jul '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56264 ) Change subject: drivers/usb/acpi: Fix usb_acpi_get_pld ...................................................................... drivers/usb/acpi: Fix usb_acpi_get_pld Commit 8e885a57b13a2 introduced a new function and it Coverity found 2 bugs in it: 1) Use before NULL check 2) Incorrect size passed to memcpy() Found-by: Coverity CID 1458231 Found-by: Coverity CID 1458232 Change-Id: I424ae185f544c13c0638ff57c097d784265f2848 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/usb/acpi/usb_acpi.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/56264/1 diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index a0dadff..395f069 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -125,14 +125,15 @@ bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld) { - struct drivers_usb_acpi_config *config = usb_device->chip_info; + struct drivers_usb_acpi_config *config; if (!usb_device || !usb_device->chip_info || usb_device->chip_ops != &drivers_usb_acpi_ops) return false; + config = usb_device->chip_info; if (config->use_custom_pld) - memcpy(pld, &config->custom_pld, sizeof(pld)); + memcpy(pld, &config->custom_pld, sizeof(*pld)); else acpi_pld_fill_usb(pld, config->type, &config->group); -- To view, visit https://review.coreboot.org/c/coreboot/+/56264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424ae185f544c13c0638ff57c097d784265f2848 Gerrit-Change-Number: 56264 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: use mca_clear_status function instead of open coding
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56259 to look at the new patch set (#2). Change subject: src: use mca_clear_status function instead of open coding ...................................................................... src: use mca_clear_status function instead of open coding Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/common/block/cpu/cpulib.c 9 files changed, 11 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56259/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Gerrit-Change-Number: 56259 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by build bot (Jenkins) (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Angel Pons, Michal Motyl. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Patch Set 3: (2 comments) File util/sconfig/main.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123974): https://review.coreboot.org/c/coreboot/+/51180/comment/720cf6d6_60c97f13 PS3, Line 1311: fprintf(head, "extern DEVTREE_CONST void *const __pci_%d_%02x_%d_config;\n", line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123974): https://review.coreboot.org/c/coreboot/+/51180/comment/bbe5fbae_1d5cdfcc PS3, Line 1313: fprintf(fil, "DEVTREE_CONST void *const __pci_%d_%02x_%d_config = &%s_info_%d;\n", line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 3 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 17:00:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julian Schroeder. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56188 ) Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56188/comment/f0acb87b_405cd926 PS4, Line 9: CollaborativeProcessorPerformanceControl : See also: uefi.org/specifications : This leverages the existing CPPC support and adds a : cppc init for AMD/Cezanne. : maybe: This leverages the existing Collaborative Processor Performance Control (CPPC) support and adds CPPC init for AMD/Cezanne. File src/soc/amd/cezanne/cppc.c: https://review.coreboot.org/c/coreboot/+/56188/comment/a250a63f_804d7159 PS4, Line 168: int unsigned int? File src/soc/amd/cezanne/include/soc/cppc.h: PS4: i'd put the msr number and bit defines in oc/amd/cezanne/include/soc/msr.h -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 4 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Subrata Banik (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Michał Żygowski, Furquan Shaikh, Marshall Dawson, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/53ec4c0f_aa171cb7 PS3, Line 14: looks_like_fsp_header can we change this code like below? 1. Read FSP_INFO_HEADER.SpecVersion 2. If (FSP_INFO_HEADER.SpecVersion == 0x20) // FSP 2.0 Header - Check if FSP_INFO_HEADER.HeaderLength is either 0x48 and 0x4C as you might have some platform where EDK2 latest version cause FSP header length appear as 0x4C rather 0x48 as per spec 2.0. Consider we accommodate the violation as well. 3. If (FSP_INFO_HEADER.SpecVersion == 0x22) // FSP 2.2 Header - Check if FSP_INFO_HEADER.HeaderLength is 0x4c 4. Else return false and print error ? -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:57:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Martin Roth (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Michał Żygowski, Furquan Shaikh, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/c099fc66_261a8626 PS2, Line 13: however, some FSP 2.0 variants have it as well. > The FSP header revision field may also be looked at to check what size to expect. […] I think the real solution is a fix from intel, either to EDK2 or the FSP spec. Until that happens though, I think we need a solution for the current situation. Maybe we put a TODO here? Furquan, would you rather a fix in our version of the EDK? I don't like that solution as much in general, because then Intel's FSPs built from the 202011 wouldn't work with coreboot, but I'm open to ideas. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:54:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Mariusz Szafrański (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Angel Pons, Michal Motyl. Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: As discussed previously via email RFC/initial draft https://review.coreboot.org/c/coreboot/+/56263 -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 3 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:46:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Subrata Banik (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Michał Żygowski, Martin Roth, Furquan Shaikh, Marshall Dawson, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/6a86d716_12e1fe39 PS2, Line 13: however, some FSP 2.0 variants have it as well. > The FSP header revision field may also be looked at to check what size to expect. […] looks like we are always overriding this from FSP package since we introduced FSP2.2 spec. Unless we align the FSP header spec along with new EDK2 version, we might have problem with looks_like_fsp_header() -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:46:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] Intel IIO split stack - multidomain approach
by Mariusz Szafrański (Code Review) 13 Jul '21

13 Jul '21

Mariusz Szafrański has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56263 ) Change subject: [RFC] Intel IIO split stack - multidomain approach ...................................................................... [RFC] Intel IIO split stack - multidomain approach RFC/initial proposal on how to support Intel split IIO architecture in coreboot Change-Id: I38ac830ee05866a09c5661ec48fab96af8135f44 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> --- A Documentation/RFC/intel-iio-split-stack.md 1 file changed, 91 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/56263/1 diff --git a/Documentation/RFC/intel-iio-split-stack.md b/Documentation/RFC/intel-iio-split-stack.md new file mode 100644 index 0000000..740a64c --- /dev/null +++ b/Documentation/RFC/intel-iio-split-stack.md @@ -0,0 +1,91 @@ += Intel split IIO design support in coreboot + +== Status of this document + +This document is RFC/initial proposal how to implement split IIO in coreboot. +First attempt to support new design is already present in Xeon SP code. +This document is proposal to use another approach to handle new design. +Please fill free to comment, present your valuable opinions and additional ideas. + +== Introduction. What is split IIO? + +IIO - Integrated I/O +The processor Integrated I/O is the next generation I/O offering a very high bandwidth +interface while maintaining software compatibility with existing chipset solutions. + +Let`s describe it in high level and simplified version without going into details. + +In the past Intel`s products there was one root bus (bus 0) coming out "directly" from CPU. +Additional (secondary/subordinate) busses were connected via bridge devices. +Latest Intel`s products (CooperLake SP, SkyLake SP and upcoming) extends above legacy +architecture by introducing additional root busses coming out directly from cpu. +One root bus with all busses and devices connected to it is called "stack". +We have multiple stacks to support in coreboot. + +== split IIO vs. coreboot + +Current coreboot has support for legacy architecture with only one root bus (one stack). +There is a need to extend it to support new design. Due to the split IIO design, programming +of system resources is quite different from past products. In legacy case full IO/MMIO range +was assigned to root bus 0. In new design there is a need to split available resource ranges +between each stack. + +== Current state + +There exists initial implementation of new design in Xeon SP code. But it is not final +nor complete. + +== How to support new design in coreboot? + +* 1. Continue Xeon SP like approach +* 2. Introduce additional virtual root bridge device which will connect CPU to root busses +* 3. Reuse existing domain to encapsulate each stack. (multidomain approach) + +AFAIK first one Xeon SP like code has many implementation difficulties to overcome +and is not "clear" enough solution. + +Previously we have tried to follow second option - added new virtual root bridge device to +connect each root bus to cpu. This approach added high level of complexity to the code. This +approach was abandoned and never come to fully working state. + +We followed third option finally - multidomain approach. It has very small impact on and +seamlessly integrates into current coreboot code without need for huge changes to core parts. +Currently we have almost ready to upstream and fully working code for new SoC based on this +approach. + +== Multidomain approach - implementation details + +=== devicetree.cb + +Use multiple domains in devicetree.cb. Each stack has its own domain + + device domain 0 on //stack 0 + device pci 00.0 on end + ....... + end + device domain 1 on //stack 1 + device pci 00.0 on end + ....... + end + ...... + +Note: +CB:51180 - Small change is needed to util/sconfig to support multiple domains. + +=== Resource allocation + +We need to split available full resource range IO/MMIO between each stack. +This is done internally by FSP. Information about ranges available for each stack is exposed +via UDS hob (universal data hob). In domain level read_resources function we are assigning +available ranges to each domain then allow built in resource allocator to freely assign +resources to devices within available ranges. + +=== Above 4G resources + +Small change is needed to allow resource allocation for both below and above 4G barrier. + +== Summary + +Presented above multidomain concept to support split IIO design in coreboot allowed us to +prepare fully working POC for upcoming SoC. It is almost ready for upstreaming. + -- To view, visit https://review.coreboot.org/c/coreboot/+/56263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ac830ee05866a09c5661ec48fab96af8135f44 Gerrit-Change-Number: 56263 Gerrit-PatchSet: 1 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Michał Żygowski (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/b0841718_354acba4 PS2, Line 13: however, some FSP 2.0 variants have it as well. > The FSP header has a length field. […] The FSP header revision field may also be looked at to check what size to expect. So to safecheck the length doesn't go out of control we may check if the revision does not match expected value in length, simply warn on the console. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 16:37:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2021