coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/picasso/mca: add missing types.h include
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56282 ) Change subject: soc/amd/picasso/mca: add missing types.h include ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Gerrit-Change-Number: 56282 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 22:41:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Replace `def_bool` with `bool`
by Felix Singer (Code Review) 14 Jul '21

14 Jul '21

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52806 ) Change subject: mb/kontron/bsl6: Replace `def_bool` with `bool` ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I475c56464cd9e194c575d120b6ce15c8445103b6 Gerrit-Change-Number: 52806 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/clevo: Replace `def_bool` with `bool`
by Felix Singer (Code Review) 14 Jul '21

14 Jul '21

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52805 ) Change subject: mb/clevo: Replace `def_bool` with `bool` ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3558820ae45090b5f3cf494badde9e37ca2721bb Gerrit-Change-Number: 52805 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/*/mca: factor out BERT entry generation to soc/amd/common
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56283 ) Change subject: soc/amd/*/mca: factor out BERT entry generation to soc/amd/common ...................................................................... soc/amd/*/mca: factor out BERT entry generation to soc/amd/common Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/mca/Makefile.inc A src/soc/amd/common/block/cpu/mca/mca_bert.c A src/soc/amd/common/block/cpu/mca/mcax_bert.c M src/soc/amd/common/block/include/amdblocks/mca.h M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 6 files changed, 268 insertions(+), 256 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/56283/1 diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.inc b/src/soc/amd/common/block/cpu/mca/Makefile.inc index 0aa47e1..5c1d2c5 100644 --- a/src/soc/amd/common/block/cpu/mca/Makefile.inc +++ b/src/soc/amd/common/block/cpu/mca/Makefile.inc @@ -1 +1,3 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON) += mca_common.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA) += mca_bert.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCAX) += mcax_bert.c diff --git a/src/soc/amd/common/block/cpu/mca/mca_bert.c b/src/soc/amd/common/block/cpu/mca/mca_bert.c new file mode 100644 index 0000000..ffd8973 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mca_bert.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> +#include <acpi/acpi.h> +#include <console/console.h> +#include <arch/bert_storage.h> +#include <cper.h> +#include <types.h> + +static inline size_t mca_report_size_reqd(void) +{ + size_t size; + + size = sizeof(acpi_generic_error_status_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_proc_generic_error_section_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_ia32x64_proc_error_section_t); + + /* Check Error */ + size += cper_ia32x64_check_sz(); + + /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); + + /* Context of MCi_CTL, MCi_STATUS, MCi_ADDR, MCi_MISC */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 4); + + /* Context of CTL_MASK */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); + + return size; +} + +static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) +{ + int error = mca_err_type(mci->sts); + + if (error == MCA_ERRTYPE_BUS) + return X86_PROCESSOR_BUS_CHK; + if (error == MCA_ERRTYPE_INT) + return X86_PROCESSOR_MS_CHK; + if (error == MCA_ERRTYPE_MEM) + return X86_PROCESSOR_CACHE_CHK; + if (error == MCA_ERRTYPE_TLB) + return X86_PROCESSOR_TLB_CHK; + + return X86_PROCESSOR_MS_CHK; /* unrecognized */ +} + +/* Fill additional information in the Generic Processor Error Section. */ +static void fill_generic_section(cper_proc_generic_error_section_t *sec, + struct mca_bank_status *mci) +{ + int type = mca_err_type(mci->sts); + + if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ + sec->error_type = GENPROC_ERRTYPE_BUS; + else if (type == MCA_ERRTYPE_INT) + sec->error_type = GENPROC_ERRTYPE_UARCH; + else if (type == MCA_ERRTYPE_MEM) + sec->error_type = GENPROC_ERRTYPE_CACHE; + else if (type == MCA_ERRTYPE_TLB) + sec->error_type = GENPROC_ERRTYPE_TLB; + else + sec->error_type = GENPROC_ERRTYPE_UNKNOWN; + sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; +} + +/* Convert an error reported by an MCA bank into BERT information to be reported + * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, + * which is the best method to report MSR context. As a result, add two + * structures: A "processor generic error" that is parsed, and an IA32/X64 one + * to capture complete information. + * + * Future work may attempt to interpret the specific Family 15h error symptoms + * found in the MCA registers. This data could enhance the reporting of the + * Processor Generic section and the failing error/check added to the + * IA32/X64 section. + */ +void build_bert_mca_error(struct mca_bank_status *mci) +{ + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *gen_entry; + acpi_hest_generic_data_v300_t *x86_entry; + cper_proc_generic_error_section_t *gen_sec; + cper_ia32x64_proc_error_section_t *x86_sec; + cper_ia32x64_proc_error_info_t *chk; + cper_ia32x64_context_t *ctx; + + if (mca_report_size_reqd() > bert_storage_remaining()) + goto failed; + + status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); + if (!status) + goto failed; + + gen_entry = acpi_hest_generic_data3(status); + gen_sec = section_of_acpientry(gen_sec, gen_entry); + + fill_generic_section(gen_sec, mci); + + x86_entry = bert_append_ia32x64(status); + x86_sec = section_of_acpientry(x86_sec, x86_entry); + + chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); + if (!chk) + goto failed; + + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MC_CTL_MASK(mci->bank), 1); + if (!ctx) + goto failed; + + return; + +failed: + /* We're here because of a hardware error, don't break something else */ + printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); +} diff --git a/src/soc/amd/common/block/cpu/mca/mcax_bert.c b/src/soc/amd/common/block/cpu/mca/mcax_bert.c new file mode 100644 index 0000000..f976158 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mcax_bert.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <amdblocks/msr_zen.h> +#include <cpu/x86/msr.h> +#include <acpi/acpi.h> +#include <console/console.h> +#include <arch/bert_storage.h> +#include <cper.h> +#include <types.h> + +/* MISC4 is the last used register in the MCAX banks of Picasso */ +#define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) + +static inline size_t mca_report_size_reqd(void) +{ + size_t size; + + size = sizeof(acpi_generic_error_status_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_proc_generic_error_section_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_ia32x64_proc_error_section_t); + + /* Check Error */ + size += cper_ia32x64_check_sz(); + + /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); + + /* Context of CTL, STATUS, ADDR, MISC0, CONFIG, IPID, SYND, RESERVED, DESTAT, DEADDR, + MISC1, MISC2, MISC3, MISC4 */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, MCAX_USED_REGISTERS_PER_BANK); + + /* Context of CTL_MASK */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); + + return size; +} + +static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) +{ + int error = mca_err_type(mci->sts); + + if (error == MCA_ERRTYPE_BUS) + return X86_PROCESSOR_BUS_CHK; + if (error == MCA_ERRTYPE_INT) + return X86_PROCESSOR_MS_CHK; + if (error == MCA_ERRTYPE_MEM) + return X86_PROCESSOR_CACHE_CHK; + if (error == MCA_ERRTYPE_TLB) + return X86_PROCESSOR_TLB_CHK; + + return X86_PROCESSOR_MS_CHK; /* unrecognized */ +} + +/* Fill additional information in the Generic Processor Error Section. */ +static void fill_generic_section(cper_proc_generic_error_section_t *sec, + struct mca_bank_status *mci) +{ + int type = mca_err_type(mci->sts); + + if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ + sec->error_type = GENPROC_ERRTYPE_BUS; + else if (type == MCA_ERRTYPE_INT) + sec->error_type = GENPROC_ERRTYPE_UARCH; + else if (type == MCA_ERRTYPE_MEM) + sec->error_type = GENPROC_ERRTYPE_CACHE; + else if (type == MCA_ERRTYPE_TLB) + sec->error_type = GENPROC_ERRTYPE_TLB; + else + sec->error_type = GENPROC_ERRTYPE_UNKNOWN; + sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; +} + +/* Convert an error reported by an MCA bank into BERT information to be reported + * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, + * which is the best method to report MSR context. As a result, add two + * structures: A "processor generic error" that is parsed, and an IA32/X64 one + * to capture complete information. + */ +void build_bert_mca_error(struct mca_bank_status *mci) +{ + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *gen_entry; + acpi_hest_generic_data_v300_t *x86_entry; + cper_proc_generic_error_section_t *gen_sec; + cper_ia32x64_proc_error_section_t *x86_sec; + cper_ia32x64_proc_error_info_t *chk; + cper_ia32x64_context_t *ctx; + + if (mca_report_size_reqd() > bert_storage_remaining()) + goto failed; + + status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); + if (!status) + goto failed; + + gen_entry = acpi_hest_generic_data3(status); + gen_sec = section_of_acpientry(gen_sec, gen_entry); + + fill_generic_section(gen_sec, mci); + + x86_entry = bert_append_ia32x64(status); + x86_sec = section_of_acpientry(x86_sec, x86_entry); + + chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); + if (!chk) + goto failed; + + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCAX_CTL_MSR(mci->bank), + MCAX_USED_REGISTERS_PER_BANK); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCA_CTL_MASK_MSR(mci->bank), 1); + if (!ctx) + goto failed; + + return; + +failed: + /* We're here because of a hardware error, don't break something else */ + printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); +} diff --git a/src/soc/amd/common/block/include/amdblocks/mca.h b/src/soc/amd/common/block/include/amdblocks/mca.h index 16b016b..7cead26 100644 --- a/src/soc/amd/common/block/include/amdblocks/mca.h +++ b/src/soc/amd/common/block/include/amdblocks/mca.h @@ -3,7 +3,15 @@ #ifndef AMD_BLOCK_MCA_H #define AMD_BLOCK_MCA_H +#include <cpu/x86/msr.h> + +struct mca_bank_status { + unsigned int bank; + msr_t sts; +}; + void check_mca(void); void mca_check_all_banks(void); +void build_bert_mca_error(struct mca_bank_status *mci); #endif /* AMD_BLOCK_MCA_H */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 074f313..9c02806 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -2,138 +2,9 @@ #include <amdblocks/mca.h> #include <amdblocks/msr_zen.h> -#include <amdblocks/reset.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> -#include <acpi/acpi.h> #include <console/console.h> -#include <arch/bert_storage.h> -#include <cper.h> -#include <types.h> - -/* MISC4 is the last used register in the MCAX banks of Picasso */ -#define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) - -struct mca_bank_status { - unsigned int bank; - msr_t sts; -}; - -static inline size_t mca_report_size_reqd(void) -{ - size_t size; - - size = sizeof(acpi_generic_error_status_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_proc_generic_error_section_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_ia32x64_proc_error_section_t); - - /* Check Error */ - size += cper_ia32x64_check_sz(); - - /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); - - /* Context of CTL, STATUS, ADDR, MISC0, CONFIG, IPID, SYND, RESERVED, DESTAT, DEADDR, - MISC1, MISC2, MISC3, MISC4 */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, MCAX_USED_REGISTERS_PER_BANK); - - /* Context of CTL_MASK */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); - - return size; -} - -static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) -{ - int error = mca_err_type(mci->sts); - - if (error == MCA_ERRTYPE_BUS) - return X86_PROCESSOR_BUS_CHK; - if (error == MCA_ERRTYPE_INT) - return X86_PROCESSOR_MS_CHK; - if (error == MCA_ERRTYPE_MEM) - return X86_PROCESSOR_CACHE_CHK; - if (error == MCA_ERRTYPE_TLB) - return X86_PROCESSOR_TLB_CHK; - - return X86_PROCESSOR_MS_CHK; /* unrecognized */ -} - -/* Fill additional information in the Generic Processor Error Section. */ -static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank_status *mci) -{ - int type = mca_err_type(mci->sts); - - if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ - sec->error_type = GENPROC_ERRTYPE_BUS; - else if (type == MCA_ERRTYPE_INT) - sec->error_type = GENPROC_ERRTYPE_UARCH; - else if (type == MCA_ERRTYPE_MEM) - sec->error_type = GENPROC_ERRTYPE_CACHE; - else if (type == MCA_ERRTYPE_TLB) - sec->error_type = GENPROC_ERRTYPE_TLB; - else - sec->error_type = GENPROC_ERRTYPE_UNKNOWN; - sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; -} - -/* Convert an error reported by an MCA bank into BERT information to be reported - * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, - * which is the best method to report MSR context. As a result, add two - * structures: A "processor generic error" that is parsed, and an IA32/X64 one - * to capture complete information. - */ -static void build_bert_mca_error(struct mca_bank_status *mci) -{ - acpi_generic_error_status_t *status; - acpi_hest_generic_data_v300_t *gen_entry; - acpi_hest_generic_data_v300_t *x86_entry; - cper_proc_generic_error_section_t *gen_sec; - cper_ia32x64_proc_error_section_t *x86_sec; - cper_ia32x64_proc_error_info_t *chk; - cper_ia32x64_context_t *ctx; - - if (mca_report_size_reqd() > bert_storage_remaining()) - goto failed; - - status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); - if (!status) - goto failed; - - gen_entry = acpi_hest_generic_data3(status); - gen_sec = section_of_acpientry(gen_sec, gen_entry); - - fill_generic_section(gen_sec, mci); - - x86_entry = bert_append_ia32x64(status); - x86_sec = section_of_acpientry(x86_sec, x86_entry); - - chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); - if (!chk) - goto failed; - - ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCAX_CTL_MSR(mci->bank), - MCAX_USED_REGISTERS_PER_BANK); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCA_CTL_MASK_MSR(mci->bank), 1); - if (!ctx) - goto failed; - - return; - -failed: - /* We're here because of a hardware error, don't break something else */ - printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); -} static const char *const mca_bank_name[] = { [0] = "Load-store unit", diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 67efdfd..165d41f 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -5,136 +5,9 @@ #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> -#include <acpi/acpi.h> #include <console/console.h> -#include <arch/bert_storage.h> -#include <cper.h> #include <types.h> -struct mca_bank_status { - unsigned int bank; - msr_t sts; -}; - -static inline size_t mca_report_size_reqd(void) -{ - size_t size; - - size = sizeof(acpi_generic_error_status_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_proc_generic_error_section_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_ia32x64_proc_error_section_t); - - /* Check Error */ - size += cper_ia32x64_check_sz(); - - /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); - - /* Context of MCi_CTL, MCi_STATUS, MCi_ADDR, MCi_MISC */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 4); - - /* Context of CTL_MASK */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); - - return size; -} - -static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) -{ - int error = mca_err_type(mci->sts); - - if (error == MCA_ERRTYPE_BUS) - return X86_PROCESSOR_BUS_CHK; - if (error == MCA_ERRTYPE_INT) - return X86_PROCESSOR_MS_CHK; - if (error == MCA_ERRTYPE_MEM) - return X86_PROCESSOR_CACHE_CHK; - if (error == MCA_ERRTYPE_TLB) - return X86_PROCESSOR_TLB_CHK; - - return X86_PROCESSOR_MS_CHK; /* unrecognized */ -} - -/* Fill additional information in the Generic Processor Error Section. */ -static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank_status *mci) -{ - int type = mca_err_type(mci->sts); - - if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ - sec->error_type = GENPROC_ERRTYPE_BUS; - else if (type == MCA_ERRTYPE_INT) - sec->error_type = GENPROC_ERRTYPE_UARCH; - else if (type == MCA_ERRTYPE_MEM) - sec->error_type = GENPROC_ERRTYPE_CACHE; - else if (type == MCA_ERRTYPE_TLB) - sec->error_type = GENPROC_ERRTYPE_TLB; - else - sec->error_type = GENPROC_ERRTYPE_UNKNOWN; - sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; -} - -/* Convert an error reported by an MCA bank into BERT information to be reported - * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, - * which is the best method to report MSR context. As a result, add two - * structures: A "processor generic error" that is parsed, and an IA32/X64 one - * to capture complete information. - * - * Future work may attempt to interpret the specific Family 15h error symptoms - * found in the MCA registers. This data could enhance the reporting of the - * Processor Generic section and the failing error/check added to the - * IA32/X64 section. - */ -static void build_bert_mca_error(struct mca_bank_status *mci) -{ - acpi_generic_error_status_t *status; - acpi_hest_generic_data_v300_t *gen_entry; - acpi_hest_generic_data_v300_t *x86_entry; - cper_proc_generic_error_section_t *gen_sec; - cper_ia32x64_proc_error_section_t *x86_sec; - cper_ia32x64_proc_error_info_t *chk; - cper_ia32x64_context_t *ctx; - - if (mca_report_size_reqd() > bert_storage_remaining()) - goto failed; - - status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); - if (!status) - goto failed; - - gen_entry = acpi_hest_generic_data3(status); - gen_sec = section_of_acpientry(gen_sec, gen_entry); - - fill_generic_section(gen_sec, mci); - - x86_entry = bert_append_ia32x64(status); - x86_sec = section_of_acpientry(x86_sec, x86_entry); - - chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); - if (!chk) - goto failed; - - ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MC_CTL_MASK(mci->bank), 1); - if (!ctx) - goto failed; - - return; - -failed: - /* We're here because of a hardware error, don't break something else */ - printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); -} - static const char *const mca_bank_name[] = { [0] = "Load-store unit", [1] = "Instruction fetch unit", -- To view, visit https://review.coreboot.org/c/coreboot/+/56283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Gerrit-Change-Number: 56283 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/mca: add missing types.h include
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56282 ) Change subject: soc/amd/picasso/mca: add missing types.h include ...................................................................... soc/amd/picasso/mca: add missing types.h include Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/56282/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 97f5d0b..074f313 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -9,6 +9,7 @@ #include <console/console.h> #include <arch/bert_storage.h> #include <cper.h> +#include <types.h> /* MISC4 is the last used register in the MCAX banks of Picasso */ #define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/56282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Gerrit-Change-Number: 56282 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Create eNEM Kconfig for Alder Lake
by Tim Wawrzynczak (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56090 ) Change subject: soc/intel/alderlake: Create eNEM Kconfig for Alder Lake ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/56090/comment/4fccae83_08ce6216 PS3, Line 88: default y if !INTEL_CAR_NEM Not sure we want this, given the issues with various steppings -- To view, visit https://review.coreboot.org/c/coreboot/+/56090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Gerrit-Change-Number: 56090 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 22:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
by Tim Wawrzynczak (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Nick Vaccaro, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51374 ) Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87 ...................................................................... Patch Set 13: Code-Review+1 (1 comment) Patchset: PS13: Looks OK to me, let others look too -- To view, visit https://review.coreboot.org/c/coreboot/+/51374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Gerrit-Change-Number: 51374 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 22:36:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Furquan Shaikh (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (2 comments) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/a884f1e3_c797371a PS2, Line 13: however, some FSP 2.0 variants have it as well. > I don't think we should have the header length hardcoded, and should instead rely on that length field (to a reasonable value), even if it's longer than the structure we're using. Just treat anything past the end of the structure as reserved. Reading the spec again and rethinking how this is handled, I agree with what you said about not assuming a hardcoded header length for a specific version. IIUC, EDK2 FSP2Pkg is supposed to work with different FSP 2.x variants. Given that, as you mentioned, we will have to ensure that the header length is set to a reasonable value and treat anything beyond the expected length as reserved. What do you think about this: 1. Rename FSP_HDR_LEN to FSP_MIN_HDR_LEN or better convert this into a helper: ``` static uint32_t fsp_hdr_get_expected_min_length(void) { if (CONFIG(PLATFORM_USES_FSP2_2)) return 76; else if (CONFIG(PLATFORM_USES_FSP2_1)) return 72; else if (CONFIG(PLATFORM_USES_FSP2_0)) return 72; else return dead_code_t(uint32_t); } ``` 2. In `looks_like_fsp_header()`, ensure that `fsp_hdr_length >= fsp_hdr_get_expected_min_length()`, else fail. This will sanity check that the header is not too small for the specific header revision and any extra bytes at the end of header will automatically be ignored. File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/988554c5_0e11b758 PS3, Line 14: looks_like_fsp_header > Thanks Subrata! Posted a response here: https://review.coreboot.org/c/coreboot/+/56190/comment/b1cfa114_4da88906/. I think the reason why EDK2 hasn't been updated is because it is compatible with different 2.x variants. Hence, the default is set to 2.0 and it is upto the FSP package to update the header version PCD if it supports a newer revision. It would be good to get a confirmation if that understanding/expectation is correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 22:31:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo: Replace `def_bool` with `bool`
by Michael Niewöhner (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Felix Singer. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52805 ) Change subject: mb/clevo: Replace `def_bool` with `bool` ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3558820ae45090b5f3cf494badde9e37ca2721bb Gerrit-Change-Number: 52805 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Tue, 13 Jul 2021 22:26:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: factor out check_mca to common code
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56281 ) Change subject: soc/amd: factor out check_mca to common code ...................................................................... soc/amd: factor out check_mca to common code Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/mca.c M src/soc/amd/common/block/cpu/Kconfig A src/soc/amd/common/block/cpu/mca/Makefile.inc A src/soc/amd/common/block/cpu/mca/mca_common.c M src/soc/amd/common/block/include/amdblocks/mca.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/mca.c 10 files changed, 41 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/56281/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 8f93512..71cca6a 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c index a8d9702..68fae29 100644 --- a/src/soc/amd/cezanne/mca.c +++ b/src/soc/amd/cezanne/mca.c @@ -1,18 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> -#include <cpu/x86/msr.h> -static void mca_check_all_banks(void) +void mca_check_all_banks(void) { /* TODO: Implement MCAX register checking and BERT table generation. */ } - -/* Check the Machine Check Architecture Extension registers */ -void check_mca(void) -{ - mca_check_all_banks(); - /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are - aliases, we can use either set of registers. */ - mca_clear_status(); -} diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 1437326..79e011f 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -26,6 +26,26 @@ endif # SOC_AMD_COMMON_BLOCK_NONCAR +config SOC_AMD_COMMON_BLOCK_MCA_COMMON + bool + help + Add common machine check architecture support. Do not select this + in the SoC's Kconfig; select either SOC_AMD_COMMON_BLOCK_MCA or + SOC_AMD_COMMON_BLOCK_MCAX which will select this one. + +config SOC_AMD_COMMON_BLOCK_MCA + bool + select SOC_AMD_COMMON_BLOCK_MCA_COMMON + help + Add IA32 machine check architecture (MCA) support for pre-Zen CPUs. + +config SOC_AMD_COMMON_BLOCK_MCAX + bool + select SOC_AMD_COMMON_BLOCK_MCA_COMMON + help + Add extended machine check architecture (MCAX) support for AMD family + 17h, 19h and possibly newer CPUs. + config SOC_AMD_COMMON_BLOCK_SMM bool help diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.inc b/src/soc/amd/common/block/cpu/mca/Makefile.inc new file mode 100644 index 0000000..0aa47e1 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON) += mca_common.c diff --git a/src/soc/amd/common/block/cpu/mca/mca_common.c b/src/soc/amd/common/block/cpu/mca/mca_common.c new file mode 100644 index 0000000..fa9a531 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mca_common.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <cpu/x86/msr.h> + +/* Check the Machine Check Architecture Extension registers */ +void check_mca(void) +{ + mca_check_all_banks(); + /* mca_clear_status uses the MCA registers which can be used in both the MCA and MCAX + case */ + mca_clear_status(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/mca.h b/src/soc/amd/common/block/include/amdblocks/mca.h index 9ea29e8..16b016b 100644 --- a/src/soc/amd/common/block/include/amdblocks/mca.h +++ b/src/soc/amd/common/block/include/amdblocks/mca.h @@ -4,5 +4,6 @@ #define AMD_BLOCK_MCA_H void check_mca(void); +void mca_check_all_banks(void); #endif /* AMD_BLOCK_MCA_H */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 42c3bfc..88bff50 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 24a921a..97f5d0b 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -192,7 +192,7 @@ printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } -static void mca_check_all_banks(void) +void mca_check_all_banks(void) { struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); @@ -214,12 +214,3 @@ } } } - -/* Check the Machine Check Architecture Extension registers */ -void check_mca(void) -{ - mca_check_all_banks(); - /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are - aliases, we can use either set of registers. */ - mca_clear_status(); -} diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 821d1ee..e799ea0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -33,6 +33,7 @@ select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_MCA select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PM diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 5971d44..67efdfd 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -179,7 +179,7 @@ printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } -static void mca_check_all_banks(void) +void mca_check_all_banks(void) { struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); @@ -201,9 +201,3 @@ } } } - -void check_mca(void) -{ - mca_check_all_banks(); - mca_clear_status(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/56281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Gerrit-Change-Number: 56281 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021