coreboot-gerrit July 2021

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Change in coreboot[master]: drivers: spi_flash: Add Fast Read Dual I/O support
by Julius Werner (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Shelley Chen, Furquan Shaikh. Hello Shelley Chen, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56287 to look at the new patch set (#3). Change subject: drivers: spi_flash: Add Fast Read Dual I/O support ...................................................................... drivers: spi_flash: Add Fast Read Dual I/O support The Fast Read Dual Output and Fast Read Dual I/O commands are practically identical, the only difference being how the read address is transferred (saving a whooping 2 bytes which is totally irrelevant for the amounts of data coreboot tends to read). We originally implemented Fast Read Dual Output since it's the older command and some older Winbond chips only supported that one... but it seems that some older Macronix parts for whatever reason chose to only support Fast Read Dual I/O instead. So in order to make this work for as many parts as possible, I guess we'll have to implement both. (Also, the Macronix device ID situation is utter madness with different chips with different capabilities often having the same ID, so we basically have to make a best-effort guess to strike a trade-off between fast speeds and best chance at supporting all chips. If this turns out to be a problem later, we may have to add Kconfig overrides for this or resort to SFDP parsing, although that would defeat the whole point of trying to be fast.) BUG=b:193486682 TEST=Booted CoachZ (with Dual I/O) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 --- M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h M src/drivers/spi/winbond.c M src/include/spi_flash.h 6 files changed, 100 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/56287/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Gerrit-Change-Number: 56287 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Furquan Shaikh (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/b4cfb62d_c03451d6 PS2, Line 13: however, some FSP 2.0 variants have it as well. > I am ok with the solution you proposed above. It is better to check for a minimum length than not checking it at all. Sounds good. Let's go ahead with making that change to check for minimum expected length for a revision. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 00:18:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Nikolai Vyssotski (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/8e953b59_ff1ed33e PS2, Line 13: however, some FSP 2.0 variants have it as well. > > I don't think we should have the header length hardcoded, and should instead rely on that length f […] I agree with Martin. This is not a matter of simply reporting a different FSP version via PcdFspHeaderSpecVersion (please note that it goes to 'SpecVersion' header field - naming is somewhat misleading here). If we change it to 2.2 we are implying that our FSP is 2.2 compliant which is not the case. We are FSP 2.0 compliant right now. If we were to report a different header version it would be via 'HeaderRevision' field (FSP_HEADER_REVISION_3 macro currently) but as I mentioned before we have no authority over issuing the FSP header versions so we may have a collision if we pick an arbitrary number to indicate different FSP 2.0 header length. I am ok with the solution you proposed above. It is better to check for a minimum length than not checking it at all. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 00:09:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers: spi_flash: Add Fast Read Dual I/O support
by build bot (Jenkins) (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Shelley Chen, Furquan Shaikh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56287 ) Change subject: drivers: spi_flash: Add Fast Read Dual I/O support ...................................................................... Patch Set 2: (1 comment) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124081): https://review.coreboot.org/c/coreboot/+/56287/comment/2451e62b_4d3f5c31 PS2, Line 87: /* Only the very first byte (opcode) is transfered in "single" mode. */ 'transfered' may be misspelled - perhaps 'transferred'? -- To view, visit https://review.coreboot.org/c/coreboot/+/56287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Gerrit-Change-Number: 56287 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 00:06:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI
by Thejaswani Putta (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Maulik V Vaghela, Balaji Manigandan, Bernardo Perez Priego, Thejaswani Putta. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Cliff Huang, Maulik V Vaghela, Selma Bensaid, Balaji Manigandan, Bernardo Perez Priego, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54023 to look at the new patch set (#8). Change subject: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI ...................................................................... mb/intel/adlrvp_m: Enable CR50 TPM support over SPI Add Kconfig options and enable TPM device in devicetree BUG=None TEST=Booted the image and checked the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Thejaswani Puta thejaswani.putta(a)intel.com <thejaswani.putta(a)intel.com> Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/early_gpio_m.c M src/mainboard/intel/adlrvp/gpio_m.c 4 files changed, 48 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/54023/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/54023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Gerrit-Change-Number: 54023 Gerrit-PatchSet: 8 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default
by Kangheui Won (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Martin Roth, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56289 ) Change subject: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Gerrit-Change-Number: 56289 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 23:23:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default
by Karthik Ramasubramanian (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Martin Roth, Kangheui Won, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56289 ) Change subject: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Gerrit-Change-Number: 56289 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 23:22:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/mca: add missing types.h include
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56290 ) Change subject: soc/amd/cezanne/mca: add missing types.h include ...................................................................... soc/amd/cezanne/mca: add missing types.h include Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/mca.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/56290/1 diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c index 68fae29..0c5ca48 100644 --- a/src/soc/amd/cezanne/mca.c +++ b/src/soc/amd/cezanne/mca.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> +#include <types.h> void mca_check_all_banks(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Gerrit-Change-Number: 56290 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default
by Martin Roth (Code Review) 14 Jul '21

14 Jul '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56289 ) Change subject: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default ...................................................................... mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default To be able to enable & disable PSP_verstage in the saved .config file, the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a select to a default with a prompt. BUG=182477057 TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK, verify that VBOOT_STARTS_IN_BOOTBLOCK is set. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56289/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index f9c577a..b57fc62 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -48,7 +48,14 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_SEPARATE_VERSTAGE - select VBOOT_STARTS_BEFORE_BOOTBLOCK + +config VBOOT_STARTS_BEFORE_BOOTBLOCK + bool "Enable PSP_verstage" + default y if VBOOT + +config VBOOT_STARTS_IN_BOOTBLOCK + bool + default y if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK config VBOOT_STARTS_IN_BOOTBLOCK select NO_EARLY_BOOTBLOCK_POSTCODES -- To view, visit https://review.coreboot.org/c/coreboot/+/56289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Gerrit-Change-Number: 56289 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/trogdor: Enable SPI_FLASH_MACRONIX
by Julius Werner (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Shelley Chen. Hello Shelley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56288 to review the following change. Change subject: google/trogdor: Enable SPI_FLASH_MACRONIX ...................................................................... google/trogdor: Enable SPI_FLASH_MACRONIX We may want to use that flash vendor on future variants. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f --- M src/mainboard/google/trogdor/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56288/1 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 1305088..21accde 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -30,8 +30,9 @@ select DRIVERS_TI_SN65DSI86BRIDGE select SOC_QUALCOMM_SC7180 select SPI_FLASH - select SPI_FLASH_WINBOND + select SPI_FLASH_MACRONIX select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_BUBS select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_BUBS -- To view, visit https://review.coreboot.org/c/coreboot/+/56288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f Gerrit-Change-Number: 56288 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021