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Change subject: soc/qualcomm/common/qup: Add support for QUP common driver
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> Can you put in the commit message that these files were copied over from soc/qualcomm/sc7180 so peop […]
Please merge in https://review.coreboot.org/c/coreboot/+/55955 so that we can preserve the file mv in the git history.
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Change subject: sc7180: Refactor QSPI driver
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
Please merge this with https://review.coreboot.org/c/coreboot/+/55323 to preserve the mv of the files in the git history.
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Change subject: soc/qualcomm/common/qspi: Add support for common QSPI driver
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS11:
> I meant in the commit message. […]
Actually, just merge https://review.coreboot.org/c/coreboot/+/55321 into this patch so that we preserve the mv.
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Change subject: mb/intel/adlrvp: Add TCSS USB device for ADL-M RVP
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
The purpose of this patch was to complement mechanism to set UPD 'UsbTcPortEn', this has already been covered by:
https://review.coreboot.org/c/coreboot/+/55361 -- Merged
https://review.coreboot.org/c/coreboot/+/55772 -- Merged
Should we abandon this patch?
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Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
......................................................................
Patch Set 4:
(16 comments)
File src/drivers/intel/fsp2_0/util.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/d42656b6_bb2451ab
PS4, Line 17: if (CONFIG(PLATFORM_USES_FSP2_2))
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/e6b95164_6817d412
PS4, Line 17: if (CONFIG(PLATFORM_USES_FSP2_2))
suspect code indent for conditional statements (5, 10)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/5036e9c8_01729dc8
PS4, Line 18: return 76;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/1caef222_b36a6ad5
PS4, Line 18: return 76;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/0ff6b7b6_3cbff0a6
PS4, Line 19: else if (CONFIG(PLATFORM_USES_FSP2_1))
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/01fdb559_6757652f
PS4, Line 19: else if (CONFIG(PLATFORM_USES_FSP2_1))
suspect code indent for conditional statements (5, 10)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/e4406f98_16fcc28e
PS4, Line 20: return 72;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/7bca3221_b31f2e13
PS4, Line 20: return 72;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/5f383b35_b1bd39cd
PS4, Line 21: else if (CONFIG(PLATFORM_USES_FSP2_0))
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/abfd2685_d4362189
PS4, Line 21: else if (CONFIG(PLATFORM_USES_FSP2_0))
suspect code indent for conditional statements (5, 10)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/e8ff096d_1c61130b
PS4, Line 22: return 72;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/32c9b945_00861d19
PS4, Line 22: return 72;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/fc7defb8_02a66a8c
PS4, Line 23: else
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/2bc97e18_56a30624
PS4, Line 23: else
suspect code indent for conditional statements (5, 10)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/cab4403b_b41cd06a
PS4, Line 24: return dead_code_t(uint32_t);
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124091):
https://review.coreboot.org/c/coreboot/+/56190/comment/0f3fd411_99f4822d
PS4, Line 24: return dead_code_t(uint32_t);
please, no spaces at the start of a line
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Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Marshall Dawson, Subrata Banik, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56190
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Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
......................................................................
src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
This is in preparation for migrating EDK2 to more recent version(s). In
EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0
header (FspMultiPhaseSiInitEntryOffset). This increases the length of
the header from 0x48 to 0x4c. This field is not used in coreboot yet.
Allow headers of both lengths to be accepted.
BUG=b:180186886
TEST=build/boot with both header flavors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com>
Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586
---
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/util.c
2 files changed, 18 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/56190/4
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55376 )
Change subject: spi: Limit the SPI NOR size
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS1:
> Hi Julius, […]
Yes, this patch as you uploaded here is unacceptable. If you go the route I described and don't change the coreboot FMAP, there will be no actual flash accesses beyond 8MB... depthcharge is just written to require space to buffer the whole flash in case it is needed, but if the FMAP doesn't place anything there it won't actually touch it. That's the best I can offer you. If your hardware team is still worried that this doesn't match the behavior of a real Chromebook closely enough, please ask them to build a board where the hardware actually matches a real Chromebook as well. (Also, FWIW, if you follow the discussion at b/191969933 it seems quite likely that we'll have to upgrade the real Chromebook to 16MB at some point as well, at least for some variants. Flash size can change between variants, that's a regular thing and no big deal. Just make sure the hardware is accurately represented by the code so it doesn't get confused.)
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