coreboot-gerrit July 2021

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Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
by Sridhar Siricilla (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Selma Bensaid, Sridhar Siricilla, Rizwan Qureshi, Werner Zeh. Hello build bot (Jenkins), Selma Bensaid, Sridhar Siricilla, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56073 to look at the new patch set (#6). Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon ...................................................................... mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is enableda on the system. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 --- M src/mainboard/intel/adlrvp/bootblock.c 1 file changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56073/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Gerrit-Change-Number: 56073 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Furquan Shaikh (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 4: -Code-Review (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56190/comment/b428f8b7_cae846b1 PS4, Line 12: This field is not used in coreboot yet. This is not really correct. It is used by some Intel platforms. https://review.coreboot.org/c/coreboot/+/56190/comment/e47759db_52e68659 PS4, Line 13: Allow headers of both lengths to be accepted. Can you please add the detail that the check for header length in `looks_like_fsp_header()` is updated to look for a minimum length based on version and the reason for that? File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/7bff07cc_56376d58 PS4, Line 17: if (CONFIG(PLATFORM_USES_FSP2_2)) > please, no spaces at the start of a line Please fix this and the comments below. https://review.coreboot.org/c/coreboot/+/56190/comment/7c5e1f36_a230f335 PS4, Line 36: fsp_header_length < fsp_hdr_get_expected_min_length() Can you please add a comment here explaining why header length is compared against a minimum value for the version? -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 4 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 03:31:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_name
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56277 ) Change subject: soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_name ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/stoneyridge/mca.c: https://review.coreboot.org/c/coreboot/+/56277/comment/e67544eb_11ac9b8b PS2, Line 143: Accesing non-existing MSRs causes a general protection fault. */ done -- To view, visit https://review.coreboot.org/c/coreboot/+/56277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d6a6752504d804c45b445fce7e763e80161211 Gerrit-Change-Number: 56277 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 02:48:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_name
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56277 to look at the new patch set (#4). Change subject: soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_name ...................................................................... soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_name This patch changes the way how the not implemented MCA bank 3 gets skipped. For the not implemented bank 3 the name gets set to NULL resulting in mca_is_valid_bank returning false causing the bank to get skipped. This is a preparation for commonizing the MCA(X) handing in the soc/amd sub-tree. Change-Id: I40d6a6752504d804c45b445fce7e763e80161211 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/mca.c 1 file changed, 18 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/56277/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d6a6752504d804c45b445fce7e763e80161211 Gerrit-Change-Number: 56277 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Use relative address for EFS gen2
by Kangheui Won (Code Review) 14 Jul '21

14 Jul '21

Kangheui Won has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/55211 ) Change subject: amdfwtool: Use relative address for EFS gen2 ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/55211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Gerrit-Change-Number: 55211 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "amdfwtool: Use relative address for EFS gen2"
by Kangheui Won (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Bao Zheng, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Hello Bao Zheng, build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56131 to review the following change. Change subject: Revert "amdfwtool: Use relative address for EFS gen2" ...................................................................... Revert "amdfwtool: Use relative address for EFS gen2" This reverts commit 0fc87e31e0b9ad15dd199fe96189a2ade6abf240. Reason for revert: Breaks psp_verstage in guybrush BUG=b:182477057 Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da --- M util/amdfwtool/amdfwtool.c 1 file changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/56131/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 9299aec..1e75278 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -343,12 +343,11 @@ typedef struct _context { char *rom; /* target buffer, size of flash device */ uint32_t rom_size; /* size of flash device */ - uint32_t abs_address; /* produce absolute or relative address */ uint32_t current; /* pointer within flash & proxy buffer */ } context; #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) -#define RUN_OFFSET(ctx, offset) ((ctx).abs_address ? RUN_BASE(ctx) + (offset) : (offset)) +#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) @@ -1537,6 +1536,8 @@ romsig_offset = ctx.current = dir_location - rom_base_address; else romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; + printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", + RUN_CURRENT(ctx)); amd_romsig = BUFF_OFFSET(ctx, romsig_offset); amd_romsig->signature = EMBEDDED_FW_SIGNATURE; @@ -1555,13 +1556,6 @@ fprintf(stderr, "WARNING: No SOC name specified.\n"); } - if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN) - ctx.abs_address = 0; - else - ctx.abs_address = 1; - printf(" AMDFWTOOL Using firmware directory location of %s address: 0x%08x\n", - ctx.abs_address == 1 ? "absolute" : "relative", RUN_CURRENT(ctx)); - integrate_firmwares(&ctx, amd_romsig, amd_fw_table); ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Gerrit-Change-Number: 56131 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/mca: factor out mca_has_expected_bank_count
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56294 ) Change subject: soc/amd/picasso/mca: factor out mca_has_expected_bank_count ...................................................................... soc/amd/picasso/mca: factor out mca_has_expected_bank_count To factor out the rest of the common MCAX code, mca_bank_name[] may only be accessed by accessor functions, so implement this for the last place that still accessed mca_bank_name[] directly. Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56294/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 3c5b63f..c41708c 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -33,6 +33,11 @@ [22] = "PIE", }; +static bool mca_has_expected_bank_count(void) +{ + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); +} + static bool mca_is_valid_bank(unsigned int bank) { return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); @@ -70,7 +75,7 @@ struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); - if (ARRAY_SIZE(mca_bank_name) != num_banks) + if (!mca_has_expected_bank_count()) printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); for (unsigned int i = 0 ; i < num_banks ; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9 Gerrit-Change-Number: 56294 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/mca: factor out BERT entry generation to soc/amd/common
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56283 to look at the new patch set (#3). Change subject: soc/amd/*/mca: factor out BERT entry generation to soc/amd/common ...................................................................... soc/amd/*/mca: factor out BERT entry generation to soc/amd/common Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/mca/Makefile.inc A src/soc/amd/common/block/cpu/mca/mca_bert.c A src/soc/amd/common/block/cpu/mca/mcax_bert.c M src/soc/amd/common/block/include/amdblocks/mca.h M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 6 files changed, 268 insertions(+), 255 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/56283/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Gerrit-Change-Number: 56283 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cpu/cpulib: use mca_get_bank_count()
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56245 ) Change subject: soc/intel/common/block/cpu/cpulib: use mca_get_bank_count() ...................................................................... soc/intel/common/block/cpu/cpulib: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive, and make it constant. Change-Id: I449c74629ff16057c4559d7fd3620208230560f5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56245 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9e95b0f..a245824 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -338,12 +338,10 @@ { msr_t msr; int i; - int num_banks; + const unsigned int num_banks = mca_get_bank_count(); printk(BIOS_DEBUG, "Clearing out pending MCEs\n"); - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; for (i = 0; i < num_banks; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I449c74629ff16057c4559d7fd3620208230560f5 Gerrit-Change-Number: 56245 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/*/*_init: use mca_get_bank_count()
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56244 ) Change subject: cpu/intel/*/*_init: use mca_get_bank_count() ...................................................................... cpu/intel/*/*_init: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive, and make it constant. In the case of Intel model 2065x the mca_get_bank_count() call replaces a magic number. Change-Id: I245b15f57e77edca179e9e28965383a227617174 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56244 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c 3 files changed, 4 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2d8bd15..29c663e 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -520,10 +520,7 @@ { msr_t msr; int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; + const unsigned int num_banks = mca_get_bank_count(); /* Enable all error reporting */ msr.lo = msr.hi = ~0; diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index abf8f61..fe5ac56 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -77,10 +77,11 @@ { msr_t msr; int i; + const unsigned int num_banks = mca_get_bank_count(); msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ - for (i = 0; i < 7; i++) + for (i = 0; i < num_banks; i++) wrmsr(IA32_MC_STATUS(i), msr); } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index bfe1fa5..541cb3b 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -301,10 +301,7 @@ { msr_t msr; int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; + const unsigned int num_banks = mca_get_bank_count(); msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I245b15f57e77edca179e9e28965383a227617174 Gerrit-Change-Number: 56244 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021