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Hello build bot (Jenkins), Martin Roth, Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56213
to look at the new patch set (#3).
Change subject: payloads: FILO: Hook up autoboot options
......................................................................
payloads: FILO: Hook up autoboot options
FILO allows to configure a line to autoboot. Hook this up into
coreboot’s build system.
Change-Id: Id167e9a144bf466da87469108002672b299b702a
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M payloads/external/FILO/Kconfig
M payloads/external/FILO/Makefile
M payloads/external/Makefile.inc
3 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56213/3
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55996 )
Change subject: soc/intel/alderlake: Add support for I2C6 and I2C7
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55996/comment/566696be_f96f413c
PS7, Line 9: support for I2C6 and I2C7 is added
add support for I2C6 and I2C7.
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Change subject: drivers: spi_flash: Add Fast Read Dual I/O support
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Patch Set 3: Code-Review+2
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Change subject: soc/intel/alderlake: Add support for I2C6 and I2C7
......................................................................
Patch Set 7:
(2 comments)
This change is ready for review.
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55996/comment/54ba8e93_abc28f3f
PS6, Line 89: .slot = PCH_DEV_SLOT_SIO0,
> This is taken care in this patch: […]
Done
File src/soc/intel/alderlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/55996/comment/6467e48f_ff6be3cb
PS6, Line 86: #define PCH_DEV_I2C6 _PCH_DEV(SIO0, 0)
> Please remove duplicate entries
Done
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Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
......................................................................
Patch Set 6: Code-Review+1
(5 comments)
File src/mainboard/intel/adlrvp/bootblock.c:
https://review.coreboot.org/c/coreboot/+/56073/comment/1b5c6f9c_ef49f992
PS6, Line 13: #define SI_DESC_REGION_SZ 4096
nit: This size could be included from fmap_config.h.
But I do not insist since the size of the descriptor is fixed.
https://review.coreboot.org/c/coreboot/+/56073/comment/fb398cc4_802792d8
PS6, Line 25: check_host_write_access_desc_region
I would name it more distinct, maybe something like is_descriptor_writeable() or the like. And I guess you can drop the "host" part since it is clear here.
https://review.coreboot.org/c/coreboot/+/56073/comment/4c4fbb8e_1edb7c9f
PS6, Line 28: if (*(uint32_t *)(desc + FLASH_SIGN_OFFSET) != FLASH_VAL_SIGN) {
Would it make things more readable here if you use read32 here? Maybe something like:
if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN)
https://review.coreboot.org/c/coreboot/+/56073/comment/2676aaf2_0b15bb63
PS6, Line 36: *flmstr1
Use read32() here as well?
https://review.coreboot.org/c/coreboot/+/56073/comment/665ab6ea_5bee7fe6
PS6, Line 81: BIOS_DEBUG
Should we use a lower log level here since it is a reset now?
It just happens once, right?
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