coreboot-gerrit July 2021

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Change in coreboot[master]: libpayload: curses: Only call `serial_set_color()` with initialized v...
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Paul Menzel, Jacob Garber. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51914 ) Change subject: libpayload: curses: Only call `serial_set_color()` with initialized values ...................................................................... Patch Set 6: (1 comment) Patchset: PS4: > Looks good to me. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic63e34f2b5bc9f826db37597bebc6b20542481d7 Gerrit-Change-Number: 51914 Gerrit-PatchSet: 6 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Comment-Date: Wed, 14 Jul 2021 08:22:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GFx Device ID 0x46a6
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56026 ) Change subject: soc/intel/alderlake: Add GFx Device ID 0x46a6 ...................................................................... soc/intel/alderlake: Add GFx Device ID 0x46a6 This CL adds support for new ADL graphics Device ID 0x46a6. TEST=Build and boot Adlrvp board Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56026 Reviewed-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Meera Ravindranath: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 541d38e..f3f16fb 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3818,6 +3818,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_3 0x46a3 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_4 0x46a8 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_5 0x46b3 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 5ddc322..d811123 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -105,6 +105,7 @@ { PCI_DEVICE_ID_INTEL_ADL_P_GT2_3, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 61d39bd..b99d2a8 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -301,6 +301,7 @@ PCI_DEVICE_ID_INTEL_ADL_P_GT2_3, PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, + PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, PCI_DEVICE_ID_INTEL_ADL_S_GT1, PCI_DEVICE_ID_INTEL_ADL_M_GT1, 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/56026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Gerrit-Change-Number: 56026 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Use SPR for backing up data way and eviction mask
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56161 ) Change subject: soc/intel/common: Use SPR for backing up data way and eviction mask ...................................................................... soc/intel/common: Use SPR for backing up data way and eviction mask This patch replaces the usage of GPR (General Purpose Registers) like ECX and EBX for backing up data way and non-eviction mask with SPR (Special Purpose Registers) EDI and ESI. Purpose of this change is to ensure the safety while developers might use ECX often while doing rdmsr/wrmsr rather than making use of EDI. TEST=Able to boot JSL and TGL platform without any hang using eNEM. Change-Id: I12e0cb7bb050e4f7b17ecf30108db335d1d82ab7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56161 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 74957ab..784e8ca 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -514,15 +514,15 @@ subl $0x01, %eax set_eviction_mask: - mov %ebx, %ecx /* back up number of ways */ - mov %eax, %ebx /* back up the non-eviction mask*/ + mov %ebx, %edi /* back up number of ways */ + mov %eax, %esi /* back up the non-eviction mask*/ #if CONFIG(CAR_HAS_SF_MASKS) - mov %ecx, %edi /* use number of ways to prepare SF mask */ /* * SF mask is programmed with the double number of bits than * the number of ways */ mov $0x01, %eax + mov %edi, %ecx shl %cl, %eax shl %cl, %eax subl $0x01, %eax /* contains SF mask */ @@ -533,7 +533,6 @@ movl $IA32_CR_SF_QOS_MASK_1, %ecx xorl %edx, %edx wrmsr - mov %edi, %ecx /* restore number of ways */ #endif /* * Program MSR 0xC91 IA32_L3_MASK_1 @@ -542,10 +541,11 @@ * - If this bit is '1' - the way is not protected from eviction */ mov $0x1, %eax + mov %edi, %ecx shl %cl, %eax subl $0x01, %eax mov %eax, %ecx - mov %ebx, %eax + mov %esi, %eax xor $~0, %eax /* invert 32 bits */ and %ecx, %eax @@ -558,7 +558,7 @@ * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ - mov %ebx, %eax + mov %esi, %eax movl $IA32_L3_MASK_2, %ecx xorl %edx, %edx wrmsr -- To view, visit https://review.coreboot.org/c/coreboot/+/56161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e0cb7bb050e4f7b17ecf30108db335d1d82ab7 Gerrit-Change-Number: 56161 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Drop dead `ScanExtGfxForLegacyOpRom`
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56207 ) Change subject: soc/intel/skylake: Drop dead `ScanExtGfxForLegacyOpRom` ...................................................................... soc/intel/skylake: Drop dead `ScanExtGfxForLegacyOpRom` This devicetree option is never set and never used. Drop it. Change-Id: I9cd4733746849728b2b9f85793eace9191a97f49 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56207 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/chip.h 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 59f75bf..08d5d0f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -283,7 +283,6 @@ Display_Switchable, } PrimaryDisplay; u8 SkipExtGfxScan; - u8 ScanExtGfxForLegacyOpRom; /* GPIO IRQ Route The valid values is 14 or 15*/ u8 GpioIrqSelect; -- To view, visit https://review.coreboot.org/c/coreboot/+/56207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cd4733746849728b2b9f85793eace9191a97f49 Gerrit-Change-Number: 56207 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Rename `Rmt` devicetree setting
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56206 ) Change subject: soc/intel/skylake: Rename `Rmt` devicetree setting ...................................................................... soc/intel/skylake: Rename `Rmt` devicetree setting Rename `Rmt` to `RMT` for consistency with the UPD name. Change-Id: I905b9b65fa6c5711c6e726cc09d3cad5ba3640a1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56206 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/fsp_params.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d30547e..59f75bf 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -94,7 +94,7 @@ } SaGv; /* Enable/disable Rank Margin Tool */ - u8 Rmt; + u8 RMT; /* Disable Command TriState */ u8 CmdTriStateDis; diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index f05532c..21526e4 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -83,7 +83,7 @@ m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; + m_cfg->RMT = config->RMT; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = 0; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -- To view, visit https://review.coreboot.org/c/coreboot/+/56206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I905b9b65fa6c5711c6e726cc09d3cad5ba3640a1 Gerrit-Change-Number: 56206 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/chili: Drop ineffective `SaGv` setting
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56205 ) Change subject: mb/siemens/chili: Drop ineffective `SaGv` setting ...................................................................... mb/siemens/chili: Drop ineffective `SaGv` setting SaGv is only available on ULT/ULX processors, which use PCH-LP. Given that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it does not use ULT/ULX processors, and thus does not support SaGv. Drop the `SaGv` setting from the devicetrees, as it has no effect. Change-Id: I5be518cce08206ad149efd1665e44a7111b24202 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 52d8f1c..e49ccd7 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -2,7 +2,6 @@ chip soc/intel/cannonlake # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "0" register "PchHdaDspEnable" = "0" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 37a33e7..f22e42c 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -2,7 +2,6 @@ chip soc/intel/cannonlake # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "0" register "PchHdaDspEnable" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/56205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be518cce08206ad149efd1665e44a7111b24202 Gerrit-Change-Number: 56205 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Remove KASAN from the project ideas list
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55991 ) Change subject: Documentation: Remove KASAN from the project ideas list ...................................................................... Documentation: Remove KASAN from the project ideas list This project is already implemented and therefore should not be mentioned anymore as a new project idea in the documentation. Change-Id: I38c6e274e416b98485943d36536a57a14743945b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55991 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 0 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 141023f..2f6f738 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -66,25 +66,6 @@ ### Mentors * Timothy Pearson <tpearson(a)raptorengineering.com> -## Add Kernel Address Sanitizer functionality to coreboot -The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector. -The idea is to check every memory access (variables) for its validity -during runtime and find bugs like stack overflow or out-of-bounds accesses. -Implementing this stub into coreboot like "Undefined behavior sanitizer support" -would help to ensure code quality and make the runtime code more robust. - -### Requirements -* knowledge in the coreboot build system and the concept of stages -* the KASAN feature can be improved in a way so that the memory space needed - during runtime is not on a fixed address provided during compile time but - determined during runtime. For this to achieve a small patch to the GCC will - be helpful. Therefore minor GCC knowledge would be beneficial. -* Implementation can be initially done in QEMU and improved on different - mainboards and platforms - -### Mentors -* Werner Zeh <werner.zeh(a)gmx.net> - ## Port payloads to ARM, AArch64 or RISC-V While we have a rather big set of payloads for x86 based platforms, all other architectures are rather limited. Improve the situation by porting a payload -- To view, visit https://review.coreboot.org/c/coreboot/+/55991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38c6e274e416b98485943d36536a57a14743945b Gerrit-Change-Number: 55991 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56107 ) Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN ...................................................................... sb/intel/common: Hide IFD options if !HAVE_IFD_BIN When `HAVE_IFD_BIN` is not enabled, do not show IFD-related options. Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56107 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/southbridge/intel/common/firmware/Kconfig 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 36dde56..a1026e8 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -57,6 +57,7 @@ config ME_REGION_ALLOW_CPU_READ_ACCESS bool "Allows HOST/CPU read access to ME region" + depends on HAVE_IFD_BIN default y if SOC_INTEL_CSE_LITE_SKU default n help @@ -137,8 +138,8 @@ default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/ec.bin" choice - prompt "Protect flash regions" - default UNLOCK_FLASH_REGIONS + prompt "Protect flash regions" if HAVE_IFD_BIN + default UNLOCK_FLASH_REGIONS if HAVE_IFD_BIN help This option allows you to protect flash regions. -- To view, visit https://review.coreboot.org/c/coreboot/+/56107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56 Gerrit-Change-Number: 56107 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
by Werner Zeh (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Selma Bensaid, Sridhar Siricilla, Rizwan Qureshi. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56073 ) Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/adlrvp/bootblock.c: https://review.coreboot.org/c/coreboot/+/56073/comment/c974b091_4040eb47 PS6, Line 81: BIOS_DEBUG > This CL is not meant for production use, it is to support intermediate ADL-P SI for now. […] Understood! -- To view, visit https://review.coreboot.org/c/coreboot/+/56073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Gerrit-Change-Number: 56073 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 08:13:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [DONOTSUBMIT] build system: temporarily disable adding config to cbfs
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42820 ) Change subject: [DONOTSUBMIT] build system: temporarily disable adding config to cbfs ...................................................................... [DONOTSUBMIT] build system: temporarily disable adding config to cbfs Makes comparisons between kconfig versions easier Change-Id: I30e4988b70785b3500a5b5284d760ea209c64ec4 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42820/1 diff --git a/Makefile.inc b/Makefile.inc index 7f61a5e..a204908 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1209,9 +1209,9 @@ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) vgaroms/seavgabios.bin-type := raw -cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config -config-file := $(DOTCONFIG):defconfig -config-type := raw +# cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config +# config-file := $(DOTCONFIG):defconfig +# config-type := raw cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision revision-file := $(obj)/build.h -- To view, visit https://review.coreboot.org/c/coreboot/+/42820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30e4988b70785b3500a5b5284d760ea209c64ec4 Gerrit-Change-Number: 42820 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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