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Change subject: herobrine: sc7280: Load GSI FW in ramstage
......................................................................
herobrine: sc7280: Load GSI FW in ramstage
Load GSI FW in ramstage and make it part of RW
As part of the code clean up, update the header files of the
QUP drivers with the correct path.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org>
Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30
---
M src/mainboard/google/herobrine/bootblock.c
M src/mainboard/google/herobrine/mainboard.c
2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55964/7
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Change subject: sc7280: Refactor UART driver
......................................................................
sc7280: Refactor UART driver
Refactor UART driver by separating
common and SoC specific driver code.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org>
Change-Id: I015e21081391bfe85edf667685bf117401a9ec00
---
M src/soc/qualcomm/sc7280/Kconfig
M src/soc/qualcomm/sc7280/Makefile.inc
2 files changed, 12 insertions(+), 0 deletions(-)
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Change subject: soc/qualcomm/common/qspi: Add support for common QSPI driver
......................................................................
soc/qualcomm/common/qspi: Add support for common QSPI driver
Add common QSPI functionalities for qualcomm SoC targets.
This common QSPI driver works in master mode and provides read/write
operation for the slave devices like flash.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org>
Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9
---
A src/soc/qualcomm/common/include/soc/qspi_common.h
A src/soc/qualcomm/common/qspi.c
A src/soc/qualcomm/common/spi.c
3 files changed, 440 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/55323/13
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Change subject: soc/qualcomm/sc7280: DDR One-Time-Training Support
......................................................................
soc/qualcomm/sc7280: DDR One-Time-Training Support
One-Time-Training feature support added in Qclib stage
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org>
---
M src/mainboard/google/herobrine/chromeos.fmd
M src/soc/qualcomm/sc7280/memlayout.ld
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54352/21
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Change subject: payloads: FILO: Hook up autoboot options
......................................................................
Patch Set 3:
(1 comment)
File payloads/external/FILO/Kconfig:
https://review.coreboot.org/c/coreboot/+/56213/comment/ad9e7fe4_ac0443d9
PS3, Line 29: hda1
This is FILO’s default. Should it be changed to the nowadays more common sda1?
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Change subject: payloads: FILO: Hook up autoboot options
......................................................................
Patch Set 3:
(3 comments)
Patchset:
PS3:
> Assuming this works now?
Yes, at least in my test it did.
PS3:
Should I also hook up the autoboot delay value? (Later on, the path and delay might also be read from CBFS or NVRAM.)
File payloads/external/FILO/Makefile:
https://review.coreboot.org/c/coreboot/+/56213/comment/9ed84d64_12fb93f6
PS2, Line 39: echo "CONFIG_AUTOBOOT_FILE=$(CONFIG_FILO_AUTOBOOT_FILE)" >> filo/.config
> Oh it just looks the same because that's almost the default? :) […]
Thank you. That did the trick.
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Change subject: payloads/external/tianocore: Add build argument for 4G Decode
......................................................................
Set Ready For Review
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Change subject: mb/intel/coffeelake_rvp: Rework Kconfig
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56217/comment/6a586788_5a75b489
PS3, Line 17: Built each variant with `BUILD_TIMELESS=1` and all generated
> Right, I did not include the .config file.
Would be great if you could mention this.
File src/mainboard/intel/coffeelake_rvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/56217/comment/af6733bb_57657de7
PS3, Line 15: BOARD_INTEL_COFFEELAKE_RVP8_OPTIONS
> The linter complains about this: […]
What exactly did you try? Did you remove the type declarations from this file?
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I'd like you to reexamine a change. Please visit
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Change subject: mb/intel/coffeelake_rvp: Rework Kconfig
......................................................................
mb/intel/coffeelake_rvp: Rework Kconfig
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig that the configuration
is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical.
Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/intel/coffeelake_rvp/Kconfig
M src/mainboard/intel/coffeelake_rvp/Kconfig.name
2 files changed, 57 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56217/4
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