Attention is currently required from: Angel Pons.
Hello Felix Singer, build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/54380
to look at the new patch set (#11).
Change subject: kontron/mal10: Set up GPIOs in CPLD/EC
......................................................................
kontron/mal10: Set up GPIOs in CPLD/EC
The COMe module connector implements 8 GPIO lines from the CPLD/EC pins.
Use the Kempld GPIO driver[1] to configure these pins in accordance with
the COM Express Module Base Specification [2].
TEST = Set different logic states for the pin configured as outputs and
check them with an oscilloscope.
[1] CB:47595 , Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb
[2] page 79-81, PICMG (R) COM.0 Revision 3.0 COM Express (R) Base
Specification - March 31, 2017.
Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/54380/11
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Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55078 )
Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme
......................................................................
Patch Set 12:
(1 comment)
File src/soc/qualcomm/sc7280/sc7280_egpio.c:
https://review.coreboot.org/c/coreboot/+/55078/comment/f118cbe6_7726f3ae
PS3, Line 56: setbits32(®s->cfg, BIT(EGPIO_CFG_EN));
> Hi Taniya, was wondering if Qualcomm can respond to Julius' comment above?
>>>
The kernel should always do its own GPIO setup and not rely on firmware to prepare things correctly.
>>>
Yes you are correct Julius. But here these GPIOs cannot be accessed by CPU/APSS subsystem i.e kernel driver unless we move these GPIOs which are dedicated to the LPASS subsystem to APSS/CPU. This was a request which was asked as a feature and thus we are supporting them in CB.
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Attention is currently required from: Sean Rhodes.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56088
to look at the new patch set (#25).
Change subject: mainboard: Add Star Labs labtop series
......................................................................
mainboard: Add Star Labs labtop series
Add support for:
LabTop Mk III (kbl-r)
LabTop Mk IV (cml)
StarBook Mk V (tgl)
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I090971a9e8d2be5b08be886d00d304607304b645
---
M Documentation/distributions.md
M Documentation/mainboard/index.md
A Documentation/mainboard/starlabs/labtop.md
M MAINTAINERS
A src/mainboard/starlabs/Kconfig
A src/mainboard/starlabs/Kconfig.name
A src/mainboard/starlabs/labtop/Kconfig
A src/mainboard/starlabs/labtop/Kconfig.name
A src/mainboard/starlabs/labtop/Makefile.inc
A src/mainboard/starlabs/labtop/acpi/ec.asl
A src/mainboard/starlabs/labtop/acpi/mainboard.asl
A src/mainboard/starlabs/labtop/acpi/sleep.asl
A src/mainboard/starlabs/labtop/acpi/superio.asl
A src/mainboard/starlabs/labtop/board_info.txt
A src/mainboard/starlabs/labtop/bootblock.c
A src/mainboard/starlabs/labtop/cmos.default
A src/mainboard/starlabs/labtop/cmos.layout
A src/mainboard/starlabs/labtop/dsdt.asl
A src/mainboard/starlabs/labtop/hda_verb.c
A src/mainboard/starlabs/labtop/mainboard.c
A src/mainboard/starlabs/labtop/ramstage.c
A src/mainboard/starlabs/labtop/spd/Makefile.inc
A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex
A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex
A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex
A src/mainboard/starlabs/labtop/spd/spd.h
A src/mainboard/starlabs/labtop/spd/spd_util.c
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h
A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
A src/mainboard/starlabs/labtop/variants/cml/board.fmd
A src/mainboard/starlabs/labtop/variants/cml/data.vbt
A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
A src/mainboard/starlabs/labtop/variants/cml/devtree.c
A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/cml/gpio.c
A src/mainboard/starlabs/labtop/variants/cml/hda_verb.c
A src/mainboard/starlabs/labtop/variants/cml/include/variant/ec.h
A src/mainboard/starlabs/labtop/variants/cml/romstage.c
A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
A src/mainboard/starlabs/labtop/variants/kbl/board.fmd
A src/mainboard/starlabs/labtop/variants/kbl/data.vbt
A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
A src/mainboard/starlabs/labtop/variants/kbl/devtree.c
A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/kbl/gpio.c
A src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/ec.h
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.c
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.c
A src/mainboard/starlabs/labtop/variants/kbl/romstage.c
A src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc
A src/mainboard/starlabs/labtop/variants/tgl/board.fmd
A src/mainboard/starlabs/labtop/variants/tgl/data.vbt
A src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
A src/mainboard/starlabs/labtop/variants/tgl/devtree.c
A src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/tgl/gpio.c
A src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c
A src/mainboard/starlabs/labtop/variants/tgl/include/variant/ec.h
A src/mainboard/starlabs/labtop/variants/tgl/romstage.c
62 files changed, 3,308 insertions(+), 0 deletions(-)
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Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
......................................................................
HACK trogdor: optimize coreboot.rom for T32 flash script HACK
Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8
Signed-off-by: T Michael Turney <mturney(a)codeaurora.org>
---
M src/security/vboot/Makefile.inc
A util/qualcomm/optimize_coreboot
2 files changed, 2 insertions(+), 0 deletions(-)
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Hello build bot (Jenkins), Sandeep Maheswaram,
I'd like you to reexamine a change. Please visit
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Change subject: HACK: herobrine: Assert USB_HUB_LDO_EN HACK
......................................................................
HACK: herobrine: Assert USB_HUB_LDO_EN HACK
Some herobrine variants have USB hub powered by discrete LDO that is
controlled by GPIO_157. Assert the GPIO on boot.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org>
Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2
---
M src/mainboard/google/herobrine/mainboard.c
1 file changed, 4 insertions(+), 0 deletions(-)
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Hello build bot (Jenkins), Sajida Bhanu,
I'd like you to reexamine a change. Please visit
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Change subject: HACK: SKU2 Limit SPI NOR size to 8MB HACK
......................................................................
HACK: SKU2 Limit SPI NOR size to 8MB HACK
Limit SPI NOR size to 8MB to match with coreboot rom size by changing
number of sectors.
Change-Id: I2386f9c52677b263a972dc4041a2643d36130a1b
Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org>
---
M src/drivers/spi/winbond.c
1 file changed, 1 insertion(+), 1 deletion(-)
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Hello build bot (Jenkins), Sajida Bhanu,
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Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
......................................................................
HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
Change Addressing mode of SPI nor from 4-bytes to 3-bytes As 4-bytes not
supporting in coreboot.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4
Signed-off-by: Veerabhadrarao Badiganti <vbadigan(a)codeaurora.org>
Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org>
---
M src/drivers/spi/spi_flash.c
M src/mainboard/google/herobrine/Kconfig
2 files changed, 44 insertions(+), 0 deletions(-)
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Hello build bot (Jenkins),
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Change subject: sc7280: Increased CBFS_MCACHE size
......................................................................
sc7280: Increased CBFS_MCACHE size
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I16c41031718e1c3e41d0a128c8b254e2f6f94093
---
M src/soc/qualcomm/sc7280/memlayout.ld
1 file changed, 3 insertions(+), 3 deletions(-)
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Hello build bot (Jenkins),
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Change subject: sc7280: Differentiate TPM configuration for herobrine variants
......................................................................
sc7280: Differentiate TPM configuration for herobrine variants
fix tpm boot failures in herobrine with below upstream gerrit change
https://review.coreboot.org/c/coreboot/+/55829
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I56d3576ddc078021a7d7ad0af074e01ef982d614
---
M src/mainboard/google/herobrine/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
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