coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56311 ) Change subject: soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count ...................................................................... soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count This aligns the mca_check_all_banks implementation in the common mca.c with the one in the common mcax.c file. Do the MCA bank count check before the !is_warm_reset() check, so that a mismatch also gets printed on the cold boot path. Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/mca/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/56311/1 diff --git a/src/soc/amd/common/block/cpu/mca/mca.c b/src/soc/amd/common/block/cpu/mca/mca.c index 2d91894..b5fd6a2 100644 --- a/src/soc/amd/common/block/cpu/mca/mca.c +++ b/src/soc/amd/common/block/cpu/mca/mca.c @@ -33,6 +33,9 @@ struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); + if (!mca_has_expected_bank_count()) + printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); + if (!is_warm_reset()) return; diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 240e75d..7ca16a8 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> +#include <cpu/x86/msr.h> #include <types.h> static const char *const mca_bank_name[] = { @@ -15,6 +16,11 @@ [6] = "Floating point unit" }; +bool mca_has_expected_bank_count(void) +{ + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); +} + bool mca_is_valid_bank(unsigned int bank) { return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/56311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa Gerrit-Change-Number: 56311 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add target specific GPIO pin definitions
by Martin Roth (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Ravi kumar, Taniya Das, Julius Werner, mturney mturney. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55079 ) Change subject: sc7180: Add target specific GPIO pin definitions ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: Hey Ravi, Could you rebase these in smaller sets going forward? Testing this patch train takes the coreboot builders a really significant amount of time and prevents anyone else from getting their patches tested in the meantime. We address rebasing long patch trains in the gerrit guidelines document: https://doc.coreboot.org/getting_started/gerrit_guidelines.html?highlight=g… Run ‘make what-jenkins-does’ locally on patch trains before submitting. This helps verify that the patch train won’t tie up the jenkins builders for no reason if there are failing patches in the train. For running parallel builds, you can specify the number of cores to use by setting the the CPUS environment variable. Example: make what-jenkins-does CPUS=8 Don’t submit patch trains longer than around 20 patches unless you understand how to manage long patch trains. Long patch trains can become difficult to handle and tie up the build servers for long periods of time if not managed well. Rebasing a patch train over and over as you fix earlier patches in the train can hide comments, and make people review the code multiple times to see if anything has changed between revisions. When pushing long patch trains, it is recommended to only push the full patch train once - the initial time, and only to rebase three or four patches at a time. -- To view, visit https://review.coreboot.org/c/coreboot/+/55079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268 Gerrit-Change-Number: 55079 Gerrit-PatchSet: 15 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 16:44:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads: FILO: Hook up autoboot options
by Nico Huber (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Martin Roth, Paul Menzel, Stefan Reinauer. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56213 ) Change subject: payloads: FILO: Hook up autoboot options ...................................................................... Patch Set 3: (3 comments) Patchset: PS3: > Should I also hook up the autoboot delay value? (Later on, the path and delay might also be read fro […] Your call. File payloads/external/FILO/Kconfig: https://review.coreboot.org/c/coreboot/+/56213/comment/a3d13372_334c5867 PS3, Line 29: hda1 > This is FILO’s default. […] I find it generally hard to predict what people actually need. Is there a chance at all that somebody would leave the default? If so, sure, let's change it. https://review.coreboot.org/c/coreboot/+/56213/comment/6a9beae0_a45294b9 PS3, Line 30: help Maybe add a line that these are examples? -- To view, visit https://review.coreboot.org/c/coreboot/+/56213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id167e9a144bf466da87469108002672b299b702a Gerrit-Change-Number: 56213 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 16:10:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSR
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56310 ) Change subject: include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSR ...................................................................... include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSR Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/amd/pi/00730F01/update_microcode.c M src/include/cpu/amd/msr.h M src/soc/amd/common/block/cpu/update_microcode.c 3 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/56310/1 diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c index ccf6468..8942f01 100644 --- a/src/cpu/amd/pi/00730F01/update_microcode.c +++ b/src/cpu/amd/pi/00730F01/update_microcode.c @@ -78,7 +78,7 @@ printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id); - msr = rdmsr(MSR_PATCH_LEVEL); + msr = rdmsr(IA32_BIOS_SIGN_ID); new_patch_id = msr.lo; if (new_patch_id == m->patch_id) diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index f9d20ef..aaecfde 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -80,7 +80,6 @@ #define S3_RESUME_EIP_MSR 0xC00110E0 #define PSP_ADDR_MSR 0xc00110a2 -#define MSR_PATCH_LEVEL 0x0000008B #define CORE_PERF_BOOST_CTRL 0x15c #endif /* CPU_AMD_MSR_H */ diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index 2822d2f..6d910e7 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -49,7 +49,7 @@ printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id); - msr = rdmsr(MSR_PATCH_LEVEL); + msr = rdmsr(IA32_BIOS_SIGN_ID); new_patch_id = msr.lo; if (new_patch_id == m->patch_id) -- To view, visit https://review.coreboot.org/c/coreboot/+/56310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c Gerrit-Change-Number: 56310 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: kontron/mal10: Set up GPIOs in CPLD/EC
by Nico Huber (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Maxim Polyakov, Paul Menzel, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54380 ) Change subject: kontron/mal10: Set up GPIOs in CPLD/EC ...................................................................... Patch Set 12: Code-Review+1 (1 comment) Patchset: PS10: > The pin-out table is included in the specification of COMe modules. Please see 4. […] Interesting, I did not expect them to restrict this. -- To view, visit https://review.coreboot.org/c/coreboot/+/54380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Gerrit-Change-Number: 54380 Gerrit-PatchSet: 12 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 16:03:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios
by V Sowmya (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Bora Guvendik, Shobhit Srivastava, Selma Bensaid, Maulik V Vaghela, Vinay Kumar, Kane Chen. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54055 ) Change subject: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios ...................................................................... Patch Set 13: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/54055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d485872c8bae32f83ebf94bdaa4c6a793976ce7 Gerrit-Change-Number: 54055 Gerrit-PatchSet: 13 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:50:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
by build bot (Jenkins) (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK ...................................................................... Patch Set 57: (2 comments) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124191): https://review.coreboot.org/c/coreboot/+/50586/comment/fb4aba1b_86f4ff3e PS57, Line 508: while (1) suspect code indent for conditional statements (24, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124191): https://review.coreboot.org/c/coreboot/+/50586/comment/4385e9d7_7cf585b8 PS57, Line 529: while (1) suspect code indent for conditional statements (24, 24) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 57 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:48:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by build bot (Jenkins) (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, Julius Werner, Prasad Malisetty, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... Patch Set 24: (1 comment) File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124177): https://review.coreboot.org/c/coreboot/+/53902/comment/dc184380_a0d50239 PS24, Line 168: #define PCIE_DEV_FUNC (dev, func) {(PCI_SLOT(devfn)) | (PCI_FUNC(devfn))} Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 24 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:43:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: kontron/mal10: Set up GPIOs in CPLD/EC
by Maxim Polyakov (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54380 ) Change subject: kontron/mal10: Set up GPIOs in CPLD/EC ...................................................................... Patch Set 11: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54380/comment/0593e6a3_815477d6 PS10, Line 7: Setup > Nit: The verb is spelled with a space: *set up*. Thanks! Done https://review.coreboot.org/c/coreboot/+/54380/comment/d9c1cb9c_39049f21 PS10, Line 15: [1] CB:47595 > Please also add the Change-Id. Done Patchset: PS10: > I'm confused. […] The pin-out table is included in the specification of COMe modules. Please see 4.6 Pinout Tables in "PICMG COM.0 Revision 3.0 COM Express Base Specification - March 31, 2017", Table 4.38: "Pin List for Pin-Out Type 10", page 79 (I also added information about this to the commit message). This configuration should be taken into account when designing the carrier board. Therefore, I would prefer to keep this in the module's device tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/54380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Gerrit-Change-Number: 54380 Gerrit-PatchSet: 11 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:41:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Nikolai Vyssotski (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 5: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56190/comment/e815060b_3c3727e0 PS4, Line 12: This field is not used in coreboot yet. > This is not really correct. It is used by some Intel platforms. Done https://review.coreboot.org/c/coreboot/+/56190/comment/0d6a6baa_a756743a PS4, Line 13: Allow headers of both lengths to be accepted. > Can you please add the detail that the check for header length in `looks_like_fsp_header()` is updat […] Done File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/5a2c71ce_bd565211 PS3, Line 14: looks_like_fsp_header > I believe its kind of yes and no IMHO. […] Ack File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/177066b7_3c986bdc PS4, Line 17: if (CONFIG(PLATFORM_USES_FSP2_2)) > > please, no spaces at the start of a line […] Done https://review.coreboot.org/c/coreboot/+/56190/comment/584d368f_dc60b622 PS4, Line 36: fsp_header_length < fsp_hdr_get_expected_min_length() > Can you please add a comment here explaining why header length is compared against a minimum value f […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2021