coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: ec/starlabs: Add Star Labs ITE 5570E support
by Sean Rhodes (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Paul Menzel, Angel Pons. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55263 to look at the new patch set (#14). Change subject: ec/starlabs: Add Star Labs ITE 5570E support ...................................................................... ec/starlabs: Add Star Labs ITE 5570E support Support for Star Labs labtop series EC (TGL) proprietry firmware. ASL mirrors the v1 format and function of the AMI BIOS. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 --- A src/ec/starlabs/it5570/Kconfig A src/ec/starlabs/it5570/Makefile.inc A src/ec/starlabs/it5570/acpi/ac.asl A src/ec/starlabs/it5570/acpi/battery.asl A src/ec/starlabs/it5570/acpi/cmos.asl A src/ec/starlabs/it5570/acpi/ec.asl A src/ec/starlabs/it5570/acpi/hid.asl A src/ec/starlabs/it5570/acpi/keyboard.asl A src/ec/starlabs/it5570/acpi/lid.asl A src/ec/starlabs/it5570/acpi/thermal.asl A src/ec/starlabs/it5570/chip.h A src/ec/starlabs/it5570/ec.c A src/ec/starlabs/it5570/ec.h 13 files changed, 781 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55263/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Furquan Shaikh (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/de7b7d8e_8c6acce3 PS3, Line 14: looks_like_fsp_header > No, the moment, we switch to new EDK2 header and introduced the Multi-SI package it would expects that your bootloader and FSP all are aligned with FSP2.2 spec. And unless we do that, we are expected to see this kind of issue. isn't it ? It is basically adding an entry for the MultiSi which FSP 2.2 spec says: "Offset for the API for the optional MultiPhase processor and chipset initialization defined in Section 8.10. This value is only valid if FSP HeaderRevision is >= 5. If the value is set to 0x00000000, then this API is not available in this component." My understanding of this is - the header field is valid only when header revision is >= 5 which is when FSP version is >= 2.2. If the header field exists before that, then it is not valid and can be ignored. This means that the API is not available in the component. Thus, the consumer which is coreboot in this case will be expected to ignore that field if FSP version is not >= 2.2. What kind of issues do you expect? > I believe you have tweaked "current" with "min" to accommodate the W/A that FSP2.0 might still supports a header that length is > 72? > Very similar to what i have mentioned earlier to accommodate such W/A when you have older FSP package and latest EDK2 ? Yes, it is similar to the W/A that you had posted. But instead of checking for specific spec versions and allowing combinations of lengths for each, the idea is that: * Ensure that any bytes that will be accessed for given FSP version are valid. This can be done by ensuring that the header length is at least what is expected by the reported FSP version. If it is less, then there will be a problem because we cannot read required information from the header. * Rest of the code can freely access the bytes it wants because we have already sanity checked that the header is big enough to provide the required information. When using an older FSP version with header larger than required, coreboot will not care to look at the extra bytes. So, it should just work fine. What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 19:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/starlabs: Add model-specifc Q-events
by Sean Rhodes (Code Review) 14 Jul '21

14 Jul '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56316 ) Change subject: ec/starlabs: Add model-specifc Q-events ...................................................................... ec/starlabs: Add model-specifc Q-events Add different methods use by different models in the same EC. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ie896788ccc1b67fa9b7f0f4e3af5f0a20f022a15 --- M src/ec/starlabs/it8987/acpi/ac.asl M src/ec/starlabs/it8987/acpi/ec.asl M src/ec/starlabs/it8987/acpi/hid.asl M src/ec/starlabs/it8987/acpi/keyboard.asl M src/ec/starlabs/it8987/acpi/lid.asl 5 files changed, 55 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/56316/1 diff --git a/src/ec/starlabs/it8987/acpi/ac.asl b/src/ec/starlabs/it8987/acpi/ac.asl index 97ae147..d55724a 100644 --- a/src/ec/starlabs/it8987/acpi/ac.asl +++ b/src/ec/starlabs/it8987/acpi/ac.asl @@ -32,7 +32,11 @@ } } +#if CONFIG(BOARD_STARLABS_LABTOP_KBL) +Method (_Q0A, 0, NotSerialized) // AC Power Connected +#else Method (_QA0, 0, NotSerialized) // AC Power Connected +#endif { If (ECWR & 0x01) { @@ -43,18 +47,12 @@ \PWRS = 0 } - // 500ms delay - Not used in coreboot - // Sleep (500) Notify (BAT0, 0x81) - // Sleep (500) Notify (ADP1, 0x80) } Method(_Q0B, 0, NotSerialized) // Battery Connected { - // 500ms delay - Not used in coreboot - // Sleep (500) Notify (BAT0, 0x81) - // Sleep (500) Notify (BAT0, 0x80) } diff --git a/src/ec/starlabs/it8987/acpi/ec.asl b/src/ec/starlabs/it8987/acpi/ec.asl index 451cdf1..cf97446 100644 --- a/src/ec/starlabs/it8987/acpi/ec.asl +++ b/src/ec/starlabs/it8987/acpi/ec.asl @@ -102,16 +102,13 @@ Return (0x00) } - Name (ECOK, Zero) Method(_REG, 2, NotSerialized) { If ((Arg0 == 0x03) && (Arg1 == 0x01)) { - ECOS = 1 ECAV = 1 // Unconditionally fix up the Battery and Power State. - // Initialize the Number of Present Batteries. // 1 = Real Battery 1 is present // 2 = Real Battery 2 is present @@ -119,9 +116,6 @@ BNUM = 0 BNUM |= ((ECRD (RefOf (ECWR)) & 0x02) >> 1) - // Save the current Power State for later. - // Store (PWRS, Local0) - // Initialize the Power State. // BNUM = 0 = Virtual Power State // BNUM > 0 = Real Power State @@ -142,25 +136,17 @@ // Flag that the OS supports ACPI. \_SB.PCI0.LPCB.H_EC.ECOS = 1 } - - Name (S3OS, Zero) - Method (PTS, 1, Serialized) - { - Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) - If (ECOK) { - S3OS = ECOS - } + Method (PTS, 1, Serialized) + { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) \_SB.PCI0.LPCB.H_EC.ECOS = 0 - } + } - Method (WAK, 1, Serialized) - { - Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) - If (ECOK) { - ECOS = S3OS - } - \_SB.PCI0.LPCB.H_EC.ECOS = 1 - } + Method (WAK, 1, Serialized) + { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + \_SB.PCI0.LPCB.H_EC.ECOS = 1 + } OperationRegion (SIPR, SystemIO, 0xB2, 0x1) Field (SIPR, ByteAcc, Lock, Preserve) @@ -172,9 +158,9 @@ OperationRegion(ECF2, EmbeddedControl, 0, 0xFF) Field (ECF2, ByteAcc, Lock, Preserve) { - XXX0, 8, // EC Firmware main- version number. - XXX1, 8, // EC Firmware sub- version number. - XXX2, 8, // EC Firmware test- version number. + XXX0, 8, // EC Firmware main - version number. + XXX1, 8, // EC Firmware sub - version number. + XXX2, 8, // EC Firmware test - version number. Offset(0x06), SKID, 8, // SKU ID @@ -215,7 +201,7 @@ TER4, 8, // Thermal Sensor Register 3 (skin temperature) Offset(0x63), - TSI,4, // [0..3] 0 = SEN1 - CPU VR temperature sensor + TSI, 4, // [0..3] 0 = SEN1 - CPU VR temperature sensor // 1 = SEN2 - Heat Exchanger temperature sensor // 2 = SEN3 - Skin temperature sensor // 3 = SEN4 - Ambient temperature sensor @@ -225,14 +211,14 @@ TSHT, 8, // Thermal Sensor (N) high trip point(set default value =70) TSLT, 8, // Thermal Sensor (N) low trip point (set default value =70) TSSR, 8, // TSSR- thermal sensor status register (set bit2 =1) - // BIT0:SEN1 - CPU VR Temp Sensor Trip Flag - // BIT1:SEN2 - Fan Temp Sensor Trip Flag - // BIT2:SEN3 - Skin Temp Sensor Trip Flag - // BIT3:SEN4 - Ambient Temp Sensor Trip Flag - // BIT4:Reserved - // BIT5:Reserved - // BIT6:Reserved - // BIT7:Reserved + // BIT0: SEN1 - CPU VR Temp Sensor Trip Flag + // BIT1: SEN2 - Fan Temp Sensor Trip Flag + // BIT2: SEN3 - Skin Temp Sensor Trip Flag + // BIT3: SEN4 - Ambient Temp Sensor Trip Flag + // BIT4: Reserved + // BIT5: Reserved + // BIT6: Reserved + // BIT7: Reserved CHGR, 16, // Charge Rate Offset(0x70), @@ -244,7 +230,7 @@ Offset(0x7F), LSTE, 1, // Lid feature // BIT0LID GPI - , 7, // Reserved + , 7, // Reserved Offset(0x80), ECWR, 8, // AC & Battery status @@ -320,11 +306,11 @@ CTL7, 8, Offset(0xF0), - , 3,// BIT0 .. BIT2 Reserved - TPCC, 1,// BIT3 TypeC connection bit - , 2,// BIT4 .. BIT5 Reserved - DRMD, 1,// Bit6 Dual Role Mode. 0->DFP: Host mode; 1->UFP: Device Mode. - , 1,// BIT7 Reserved + , 3, // BIT0 .. BIT2 Reserved + TPCC, 1, // BIT3 TypeC connection bit + , 2, // BIT4 .. BIT5 Reserved + DRMD, 1, // Bit6 Dual Role Mode. 0->DFP: Host mode; 1->UFP: Device Mode. + , 1, // BIT7 Reserved } Method (ECMD, 0, Serialized) @@ -371,9 +357,11 @@ #include "ac.asl" #include "lid.asl" - // Method(_Q45) // SMM Mode - Not used in coreboot - // { - // SMB2 = 0xC1 - // } +#if CONFIG(BOARD_STARLABS_LABTOP_CML) + Method(_Q45) // SMM Mode + { + SMB2 = 0xC1 + } +#endif } } diff --git a/src/ec/starlabs/it8987/acpi/hid.asl b/src/ec/starlabs/it8987/acpi/hid.asl index 25e3cd2..0d2dc0d 100644 --- a/src/ec/starlabs/it8987/acpi/hid.asl +++ b/src/ec/starlabs/it8987/acpi/hid.asl @@ -95,88 +95,47 @@ } BTLD = One -// If ((AEAB == One)) -// { - BTS1 = 0x1F - \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) -// } -// Else -// { -// BTS1 = Zero -// } + BTS1 = 0x1F + \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) } Method (BTNE, 1, Serialized) { Store ("-----> BTNE", Debug) -// If ((AEAB == One)) -// { - BTS1 = ((Arg0 & 0x1E) | One) - \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) -// } + BTS1 = ((Arg0 & 0x1E) | One) + \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) } Method (BTNS, 0, Serialized) { Store ("-----> BTNS", Debug) -// If ((AEAB == One)) -// { - BTS1 = \_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) -// } + BTS1 = \_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) Return (BTS1) } Method (BTNC, 0, Serialized) { Store ("-----> BTNC", Debug) -// If ((AEAB == One)) -// { - Return (0x1F) -// } -// Else -// { -// Return (Zero) -// } + Return (0x1F) } Name (HEB2, Zero) Method (HEBC, 0, Serialized) { Store ("-----> HEBC", Debug) -// If ((AHDB == One)) -// { -// Return (\HEB1) -// } -// Else -// { - Return (Zero) -// } + Return (Zero) } Method (H2BC, 0, Serialized) { Store ("-----> H2BC", Debug) -// If ((AHDB == One)) -// { -// Return (\HEB1) -// } -// Else -// { - Return (Zero) -// } + Return (Zero) } Method (HEEC, 0, Serialized) { Store ("-----> HEEC", Debug) -// If ((AHDB == One)) -// { - Return (HEB2) /* \_SB_.HIDD.HEB2 */ -// } -// Else -// { -// Return (Zero) -// } + Return (HEB2) /* \_SB_.HIDD.HEB2 */ } Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method diff --git a/src/ec/starlabs/it8987/acpi/keyboard.asl b/src/ec/starlabs/it8987/acpi/keyboard.asl index f5b1d52..c39bfcf 100644 --- a/src/ec/starlabs/it8987/acpi/keyboard.asl +++ b/src/ec/starlabs/it8987/acpi/keyboard.asl @@ -33,6 +33,11 @@ \_SB.PCI0.GFX0.INCB() } +Method (_Q0E) +{ + FNLC = FNST +} + Method(_Q08) // FN lock QEvent { FNLC = FNST diff --git a/src/ec/starlabs/it8987/acpi/lid.asl b/src/ec/starlabs/it8987/acpi/lid.asl index 22e8eeb..ad02f3c 100644 --- a/src/ec/starlabs/it8987/acpi/lid.asl +++ b/src/ec/starlabs/it8987/acpi/lid.asl @@ -4,6 +4,10 @@ { Name (_HID, EisaId ("PNP0C0D")) +#if CONFIG(BOARD_STARLABS_LABTOP_KBL) + Name (_PRW, Package() { EC_GPE_SWI, 3 }) +#endif + Method (_STA, 0, NotSerialized) { DEBUG = "---> IT8987 LID: _STA" -- To view, visit https://review.coreboot.org/c/coreboot/+/56316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie896788ccc1b67fa9b7f0f4e3af5f0a20f022a15 Gerrit-Change-Number: 56316 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/starlabs: Don't use model-specific names
by Sean Rhodes (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56089 to look at the new patch set (#18). Change subject: ec/starlabs: Don't use model-specific names ...................................................................... ec/starlabs: Don't use model-specific names Use it_get_version instead of it8987_get_version to avoid code duplication Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I08c4fa7802019038cca7a7c9abfd3af52cf029c3 --- M src/ec/starlabs/it8987/Makefile.inc M src/ec/starlabs/it8987/ec.c M src/ec/starlabs/it8987/ec.h 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56089/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/56089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c4fa7802019038cca7a7c9abfd3af52cf029c3 Gerrit-Change-Number: 56089 Gerrit-PatchSet: 18 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ec: Support specific Q events for different models
by Sean Rhodes (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56089 to look at the new patch set (#17). Change subject: ec: Support specific Q events for different models ...................................................................... ec: Support specific Q events for different models Add/remove certain events that are only used on specific models that share the same EC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I08c4fa7802019038cca7a7c9abfd3af52cf029c3 --- M src/ec/starlabs/it8987/Makefile.inc M src/ec/starlabs/it8987/ec.c M src/ec/starlabs/it8987/ec.h 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56089/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/56089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c4fa7802019038cca7a7c9abfd3af52cf029c3 Gerrit-Change-Number: 56089 Gerrit-PatchSet: 17 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: sc7180: Add target specific GPIO pin definitions
by Julius Werner (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Ravi kumar, Martin Roth, Taniya Das, mturney mturney. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55079 ) Change subject: sc7180: Add target specific GPIO pin definitions ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: This has been our usual workflow on these projects so I'd like to keep it working. All these different drivers are usually worked on at the same time (and often by different people in parallel), so we can't really just start with one part, clean it up all the way and only then begin working on the other. Is there any other way we can address the builder performance issue? Maybe Jenkins could be changed to only verify the first X patches in each train or something? Would it help if we set the WIP flag when uploading and then only mark a patch as ready for review when it's ready to go in? > When pushing long patch trains, it is recommended to only push the full patch train once - the initial time, and only to rebase three or four patches at a time. I'm not really sure how this is supposed to work, maybe I'm misunderstanding something. Rebasing any patch in the train automatically rebases the ones on top of it, right? Like I said we tend to work on many of these at once so it's not really possible to only work on the ones near the top. -- To view, visit https://review.coreboot.org/c/coreboot/+/55079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268 Gerrit-Change-Number: 55079 Gerrit-PatchSet: 15 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 19:22:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src: use mca_clear_status function instead of open coding
by 9elements QA (Code Review) 14 Jul '21

14 Jul '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56259 ) Change subject: src: use mca_clear_status function instead of open coding ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 1 / 13 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/67801 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/67800 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/67799 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/67798 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/67797 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/67796 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/67795 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/67794 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/67793 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/67792 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/67791 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/67790 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/67789 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/56259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Gerrit-Change-Number: 56259 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 19:00:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: console: Handle verstage as "first non-bootblock stage"
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Nico Huber, Julius Werner. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56210 ) Change subject: console: Handle verstage as "first non-bootblock stage" ...................................................................... Patch Set 1: (1 comment) File src/console/init.c: https://review.coreboot.org/c/coreboot/+/56210/comment/cd01ee07_743824c7 PS1, Line 15: #endif > Sorry, I don't understand: What difference would it make to use ENV_INITIAL_STAGE […] For one, some stages are _pretty_ packed, e.g. verstage on google/veyron. Especially with the follow-on that takes a couple more bytes to add CBFS support, verstage is overflowing there, so cutting down on that is worthwhile. (Not to say that it should be done _this_ way, but there needs to be _some_ way) -- To view, visit https://review.coreboot.org/c/coreboot/+/56210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I494a33483e306a049aa0c8137a118644fc28177e Gerrit-Change-Number: 56210 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 18:57:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cannonlake mainboards: Set PMC as hidden in devicetree
by Nico Huber (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Matt DeVillier, Jeremy Soller, Tim Wawrzynczak, Angel Pons, Karthik Ramasubramanian. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56008 ) Change subject: cannonlake mainboards: Set PMC as hidden in devicetree ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > ``` […] We do, to reserve the P2SB BAR. I've just checked on our WIP port Roda/RW14 (CFL-H). Both devices are already hidden during enumeration. I've always set them to `hidden` in the dt (cf. Siemens/Chili), so I guess it was just missed by other developers. -- To view, visit https://review.coreboot.org/c/coreboot/+/56008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Gerrit-Change-Number: 56008 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 14 Jul 2021 18:23:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "amdfwtool: Use relative address for EFS gen2"
by Martin Roth (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Bao Zheng, Raul Rangel, Marshall Dawson, Kangheui Won, Paul Menzel, Zheng Bao, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56131 ) Change subject: Revert "amdfwtool: Use relative address for EFS gen2" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Gerrit-Change-Number: 56131 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jul 2021 18:00:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021