Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56317 )
Change subject: ec/starlabs: Add Kconfig option for including EC binary
......................................................................
ec/starlabs: Add Kconfig option for including EC binary
Add EC_STARLABS_IT_BIN option so it can be enabled from .config
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Ibb066a120bff26ac95bfaa9c61c98ae518aeabb2
---
M src/ec/starlabs/it5570/Kconfig
M src/ec/starlabs/it8987/Kconfig
2 files changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56317/1
diff --git a/src/ec/starlabs/it5570/Kconfig b/src/ec/starlabs/it5570/Kconfig
index 7651757..d395040 100644
--- a/src/ec/starlabs/it5570/Kconfig
+++ b/src/ec/starlabs/it5570/Kconfig
@@ -4,4 +4,11 @@
bool
select EC_ACPI
help
- Interface to IT8987 embedded controller principally in Star Labs notebooks.
+ Interface to IT5570 embedded controller principally in Star Labs notebooks.
+
+config EC_STARLABS_IT_BIN
+ bool "Add Star Labs EC binary file"
+ default n
+ depends on EC_STARLABS_IT8987
+ help
+ The EC binary
diff --git a/src/ec/starlabs/it8987/Kconfig b/src/ec/starlabs/it8987/Kconfig
index ba9e908..146d911 100644
--- a/src/ec/starlabs/it8987/Kconfig
+++ b/src/ec/starlabs/it8987/Kconfig
@@ -5,3 +5,10 @@
select EC_ACPI
help
Interface to IT8987 embedded controller principally in Star Labs notebooks.
+
+config EC_STARLABS_IT_BIN
+ bool "Add Star Labs EC binary file"
+ default n
+ depends on EC_STARLABS_IT8987
+ help
+ The EC binary
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Gerrit-Change-Id: Ibb066a120bff26ac95bfaa9c61c98ae518aeabb2
Gerrit-Change-Number: 56317
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 )
Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
......................................................................
Patch Set 5:
(1 comment)
File src/drivers/intel/fsp2_0/util.c:
https://review.coreboot.org/c/coreboot/+/56190/comment/b275e003_c18eab92
PS3, Line 14: looks_like_fsp_header
> > No, the moment, we switch to new EDK2 header and introduced the Multi-SI package it would expects that your bootloader and FSP all are aligned with FSP2.2 spec. And unless we do that, we are expected to see this kind of issue. isn't it ?
>
> It is basically adding an entry for the MultiSi which FSP 2.2 spec says:
>
> "Offset for the API for the optional MultiPhase processor and chipset initialization defined in Section 8.10. This value is only valid if FSP HeaderRevision is >= 5. If the value is set to 0x00000000, then this API is not available in this component."
>
> My understanding of this is - the header field is valid only when header revision is >= 5 which is when FSP version is >= 2.2. If the header field exists before that, then it is not valid and can be ignored. This means that the API is not available in the component.
Yes, you are right, and that's the reason, we didn't make calling to MultiSi mandatory unlike other FSP APIs
https://github.com/coreboot/coreboot/blob/master/src/drivers/intel/fsp2_0/s… but the only discrepancy is that, irrespective of you are considering this new API or not, inclusion of MultiSi API into your EDK2 header actually claim the FSP header size == 76 as align with FSP 2.2
Also, I could able to see May 2020 Change list suggested that HeaderRevision is actually 5 using platform override
FSP_INFO_HEADER changes
o Updated SpecVersion from 0x21 to 0x22
o Updated HeaderRevision from 4 to 5
o Added FspMultiPhaseSiInitEntryOffset
> Thus, the consumer which is coreboot in this case will be expected to ignore that field if FSP version is not >= 2.2. What kind of issues do you expect?
If we had compile type option then yes, we can say that based on HeaderRevision (PcdFspHeaderRevision) < 5, during compilation time EDK2 would drop inclusion of FspMultiPhaseSiInitEntryOffset hence the output FSP header would be 76-4 = 72. But unfortunately its static hence this kind of mismatch issue i was referring.
>
> > I believe you have tweaked "current" with "min" to accommodate the W/A that FSP2.0 might still supports a header that length is > 72?
> > Very similar to what i have mentioned earlier to accommodate such W/A when you have older FSP package and latest EDK2 ?
>
> Yes, it is similar to the W/A that you had posted. But instead of checking for specific spec versions and allowing combinations of lengths for each, the idea is that:
> * Ensure that any bytes that will be accessed for given FSP version are valid. This can be done by ensuring that the header length is at least what is expected by the reported FSP version. If it is less, then there will be a problem because we cannot read required information from the header.
> * Rest of the code can freely access the bytes it wants because we have already sanity checked that the header is big enough to provide the required information. When using an older FSP version with header larger than required, coreboot will not care to look at the extra bytes. So, it should just work fine.
>
> What do you think?
patch looks good, but only consideration point imo is that, now its easy that one could add more APIs (using EDK2 override in platform code) and can grow the FSP header beyond what spec had mentioned and bootloader won't have any way to catch that as it would always pass the min size limit.
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23172 )
Change subject: payloads/external/GRUB2: Pass the architecture to grub's configure script
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/23172/comment/d8477d10_28f1d0b7
PS6, Line 7: payloads/external/GRUB2: Pass the architecture to grub's configure script
Nit: The whole commit message could be re-wrapped to be under 72 characters per line.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56188
to look at the new patch set (#6).
Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD
......................................................................
soc/amd/cezanne: add ACPI CPPC support for AMD
This leverages the existing Collaborative Processor Performance Control
(CPPC) support and adds CPPC init for AMD/Cezanne.
Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com>
Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/cezanne/acpi.c
A src/soc/amd/cezanne/cppc.c
A src/soc/amd/cezanne/include/soc/cppc.h
M src/soc/amd/cezanne/include/soc/msr.h
5 files changed, 215 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/6
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Hello Maurice Ma, Vincent Zimmer,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: Create Universal Payload Layer (UPL) in coreboot
......................................................................
Create Universal Payload Layer (UPL) in coreboot
TEST=Able to boot to Linux OS using Tianocore payload.
Change-Id: Icb114c6da237c1b17024d061a28caef706b24eac
Signed-off-by: Guo Dong <guo.dong(a)intel.com>
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
A src/include/hob.h
M src/lib/Kconfig
M src/lib/Makefile.inc
A src/lib/build_payload_hobs.c
A src/lib/hob.c
M src/lib/selfboot.c
6 files changed, 653 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/51770/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56088
to look at the new patch set (#31).
Change subject: mainboard/starlabs: Add Star Labs labtop series
......................................................................
mainboard/starlabs: Add Star Labs labtop series
Add support for:
LabTop Mk III (kbl-r)
LabTop Mk IV (cml)
StarBook Mk V (tgl)
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I090971a9e8d2be5b08be886d00d304607304b645
---
M Documentation/distributions.md
M Documentation/mainboard/index.md
A Documentation/mainboard/starlabs/labtop.md
M MAINTAINERS
A src/mainboard/starlabs/Kconfig
A src/mainboard/starlabs/Kconfig.name
A src/mainboard/starlabs/labtop/Kconfig
A src/mainboard/starlabs/labtop/Kconfig.name
A src/mainboard/starlabs/labtop/Makefile.inc
A src/mainboard/starlabs/labtop/acpi/ec.asl
A src/mainboard/starlabs/labtop/acpi/mainboard.asl
A src/mainboard/starlabs/labtop/acpi/sleep.asl
A src/mainboard/starlabs/labtop/acpi/superio.asl
A src/mainboard/starlabs/labtop/board_info.txt
A src/mainboard/starlabs/labtop/bootblock.c
A src/mainboard/starlabs/labtop/cmos.default
A src/mainboard/starlabs/labtop/cmos.layout
A src/mainboard/starlabs/labtop/dsdt.asl
A src/mainboard/starlabs/labtop/hda_verb.c
A src/mainboard/starlabs/labtop/mainboard.c
A src/mainboard/starlabs/labtop/ramstage.c
A src/mainboard/starlabs/labtop/spd/Makefile.inc
A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex
A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex
A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex
A src/mainboard/starlabs/labtop/spd/spd.h
A src/mainboard/starlabs/labtop/spd/spd_util.c
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h
A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h
A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
A src/mainboard/starlabs/labtop/variants/cml/board.fmd
A src/mainboard/starlabs/labtop/variants/cml/data.vbt
A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
A src/mainboard/starlabs/labtop/variants/cml/devtree.c
A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/cml/gpio.c
A src/mainboard/starlabs/labtop/variants/cml/hda_verb.c
A src/mainboard/starlabs/labtop/variants/cml/include/variant/ec.h
A src/mainboard/starlabs/labtop/variants/cml/romstage.c
A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
A src/mainboard/starlabs/labtop/variants/kbl/board.fmd
A src/mainboard/starlabs/labtop/variants/kbl/data.vbt
A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
A src/mainboard/starlabs/labtop/variants/kbl/devtree.c
A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads
A src/mainboard/starlabs/labtop/variants/kbl/gpio.c
A src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/ec.h
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.c
A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.c
A src/mainboard/starlabs/labtop/variants/kbl/romstage.c
A src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc
A src/mainboard/starlabs/labtop/variants/tgl/board.fmd
A src/mainboard/starlabs/labtop/variants/tgl/data.vbt
A src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
A src/mainboard/starlabs/labtop/variants/tgl/devtree.c
A src/mainboard/starlabs/labtop/variants/tgl/gpio.c
A src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c
A src/mainboard/starlabs/labtop/variants/tgl/include/variant/ec.h
A src/mainboard/starlabs/labtop/variants/tgl/romstage.c
61 files changed, 3,295 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56088/31
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