coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/common/block/lpc: Don't disable the HOG bit
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56233 ) Change subject: soc/amd/common/block/lpc: Don't disable the HOG bit ...................................................................... soc/amd/common/block/lpc: Don't disable the HOG bit According to the AMD FCH architects, we should be using the default value for the NO_HOG bit. This fixes a problem where the SPI DMA no longer functions after the LPC init runs. BUG=b:179699789, b:192373221 TEST=Boot guybrush and see SPI DMA working Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 2586ba9..3027aae 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -61,12 +61,6 @@ /* BIT 1 is not defined in public datasheet. */ byte &= ~(1 << 1); - /* - * Keep the old way. i.e., when bus master/DMA cycle is going - * on on LPC, it holds PCI grant, so no LPC slave cycle can - * interrupt and visit LPC. - */ - byte &= ~LPC_NOHOG; pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/56233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a Gerrit-Change-Number: 56233 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Move APOB update into ramstage
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56227 ) Change subject: soc/amd/cezanne: Move APOB update into ramstage ...................................................................... soc/amd/cezanne: Move APOB update into ramstage There is no technical reason this needs to be done in romstage. Moving it into ramstage allow us (in future CLs) to use threads to pre-load the apob from SPI. BUG=b:179699789 TEST=Boot and Ezkinil and Guybrush and verify APOB update still work Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/apob/Makefile.inc M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/include/amdblocks/apob_cache.h M src/soc/amd/picasso/romstage.c 5 files changed, 4 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index b64fb4b..9e863c3 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <amdblocks/acpimmio.h> -#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <arch/cpu.h> @@ -25,7 +24,6 @@ fill_chipset_state(); fsp_memory_init(acpi_is_wakeup_s3()); - soc_update_apob_cache(); /* Fixup settings FSP-M should not be changing */ fch_disable_legacy_dma_io(); diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc index 16baf81..6e217df 100644 --- a/src/soc/amd/common/block/apob/Makefile.inc +++ b/src/soc/amd/common/block/apob/Makefile.inc @@ -1,3 +1,4 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y) romstage-y += apob_cache.c +ramstage-y += apob_cache.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index 34d5472..c41627b 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -4,6 +4,7 @@ #include <amdblocks/apob_cache.h> #include <assert.h> #include <boot_device.h> +#include <bootstate.h> #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> @@ -96,7 +97,7 @@ } /* Save APOB buffer to flash */ -void soc_update_apob_cache(void) +static void soc_update_apob_cache(void *unused) { struct apob_base_header *apob_rom; struct region_device write_rdev; @@ -183,3 +184,4 @@ */ return get_apob_nv_address(); } +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL); diff --git a/src/soc/amd/common/block/include/amdblocks/apob_cache.h b/src/soc/amd/common/block/include/amdblocks/apob_cache.h index 1d29ddc..79228e5 100644 --- a/src/soc/amd/common/block/include/amdblocks/apob_cache.h +++ b/src/soc/amd/common/block/include/amdblocks/apob_cache.h @@ -4,6 +4,5 @@ #define AMD_BLOCK_APOB_CACHE_H void *soc_fill_apob_cache(void); -void soc_update_apob_cache(void); #endif /* AMD_BLOCK_APOB_CACHE_H */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index d3ceec5..1972410 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <arch/cpu.h> @@ -27,7 +26,6 @@ post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3()); - soc_update_apob_cache(); memmap_stash_early_dram_usage(); -- To view, visit https://review.coreboot.org/c/coreboot/+/56227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Gerrit-Change-Number: 56227 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: thread: Add missing static inline
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56226 ) Change subject: thread: Add missing static inline ...................................................................... thread: Add missing static inline BUG=b:179699789 TEST=Able to compile with the rest of the patch train. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56226 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/thread.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/include/thread.h b/src/include/thread.h index a2c7ed2..da8ed72 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -59,6 +59,11 @@ #else static inline void threads_initialize(void) {} static inline int thread_run(void (*func)(void *), void *arg) { return -1; } +static inline int thread_run_until(void (*func)(void *), void *arg, boot_state_t state, + boot_state_sequence_t seq) +{ + return -1; +} static inline int thread_yield_microseconds(unsigned int microsecs) { return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/56226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3 Gerrit-Change-Number: 56226 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/apob: Fix incorrect printf format
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56225 ) Change subject: soc/amd/common/block/apob: Fix incorrect printf format ...................................................................... soc/amd/common/block/apob: Fix incorrect printf format The %p format specifier already prints out 0x, so remove the 0x from the string. I also updated the other format specifiers to use the %# syntax to print out the 0x. BUG=b:179699789 TEST=see correct format. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/56225 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/apob/apob_cache.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index 238ae7a..34d5472 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -131,7 +131,7 @@ return; } - printk(BIOS_SPEW, "Copy APOB from RAM 0x%p/0x%x to flash 0x%zx/0x%zx\n", + printk(BIOS_SPEW, "Copy APOB from RAM %p/%#x to flash %#zx/%#zx\n", apob_src_ram, apob_src_ram->size, region_offset(&region), region_sz(&region)); -- To view, visit https://review.coreboot.org/c/coreboot/+/56225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec Gerrit-Change-Number: 56225 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "amdfwtool: Use relative address for EFS gen2"
by Karthik Ramasubramanian (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Bao Zheng, Raul Rangel, Martin Roth, Marshall Dawson, Kangheui Won, Paul Menzel, Zheng Bao, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56131 ) Change subject: Revert "amdfwtool: Use relative address for EFS gen2" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Gerrit-Change-Number: 56131 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jul 2021 17:44:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "amdfwtool: Use relative address for EFS gen2"
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Bao Zheng, Raul Rangel, Martin Roth, Marshall Dawson, Kangheui Won, Paul Menzel, Zheng Bao, Felix Held. Raul Rangel has uploaded a new patch set (#2) to the change originally created by Kangheui Won. ( https://review.coreboot.org/c/coreboot/+/56131 ) Change subject: Revert "amdfwtool: Use relative address for EFS gen2" ...................................................................... Revert "amdfwtool: Use relative address for EFS gen2" This reverts commit 0fc87e31e0b9ad15dd199fe96189a2ade6abf240. Reason for revert: Breaks psp_verstage in guybrush BUG=b:182477057 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da --- M util/amdfwtool/amdfwtool.c 1 file changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/56131/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Gerrit-Change-Number: 56131 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: add basic MCA support
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56262 ) Change subject: soc/amd/cezanne: add basic MCA support ...................................................................... soc/amd/cezanne: add basic MCA support Currently the MCA support for Cezanne only clears the MCA status registers. The MCA error handling and BERT table generation will be added in subsequent patches. Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56262 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/cpu.c M src/soc/amd/cezanne/include/soc/cpu.h A src/soc/amd/cezanne/mca.c 4 files changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index fa38cc3..d68a6b6 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c +ramstage-y += mca.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index ddc49a9..5f0a5a1 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -59,6 +59,7 @@ static void zen_2_3_init(struct device *dev) { + check_mca(); setup_lapic(); set_cstate_io_addr(); diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h index 27647ad..ec83349 100644 --- a/src/soc/amd/cezanne/include/soc/cpu.h +++ b/src/soc/amd/cezanne/include/soc/cpu.h @@ -5,4 +5,6 @@ #define CEZANNE_A0_CPUID 0x00a50f00 +void check_mca(void); + #endif /* AMD_CEZANNE_CPU_H */ diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c new file mode 100644 index 0000000..7160256 --- /dev/null +++ b/src/soc/amd/cezanne/mca.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <soc/cpu.h> + +/* Check the Machine Check Architecture Extension registers */ +void check_mca(void) +{ + /* TODO: Implement MCAX register checking and BERT table generation. */ + + /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are + aliases, we can use either set of registers. */ + mca_clear_status(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b Gerrit-Change-Number: 56262 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/cpu/amd/msr: add and use MC_CTL_MASK macro
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56261 ) Change subject: include/cpu/amd/msr: add and use MC_CTL_MASK macro ...................................................................... include/cpu/amd/msr: add and use MC_CTL_MASK macro Add this macro to be able to conveniently access the MC_CTL_MASK register for each MCA bank. Also drop the unused definitions for MC1_CTL_MASK and MC4_CTL_MASK. Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/include/cpu/amd/msr.h M src/soc/amd/stoneyridge/mca.c 2 files changed, 3 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 9edea5a..55a7841 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -19,8 +19,7 @@ #define NB_CFG_MSR 0xC001001f #define FidVidStatus 0xC0010042 #define MC0_CTL_MASK 0xC0010044 -#define MC1_CTL_MASK 0xC0010045 -#define MC4_CTL_MASK 0xC0010048 +#define MC_CTL_MASK(bank) (MC0_CTL_MASK + (bank)) #define MSR_INTPEND 0xC0010055 #define MMIO_CONF_BASE 0xC0010058 #define MMIO_RANGE_EN (1 << 0) diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 598bfb5..d9aac91 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -123,8 +123,7 @@ ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); if (!ctx) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, - MC0_CTL_MASK + mci->bank, 1); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MC_CTL_MASK(mci->bank), 1); if (!ctx) goto failed; @@ -160,7 +159,7 @@ printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); msr = rdmsr(IA32_MC_CTL(bank)); printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + bank); + msr = rdmsr(MC_CTL_MASK(bank)); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Gerrit-Change-Number: 56261 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56246 ) Change subject: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr ...................................................................... include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr This MSR isn't an architectural MSR, so it shouldn't be in the common x86 MSR definition header file. From family 17h on this register has moved to a different location. Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/include/cpu/amd/msr.h M src/include/cpu/x86/msr.h M src/soc/amd/stoneyridge/mca.c 3 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index f9d20ef..9edea5a 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -18,6 +18,7 @@ #define SMM_LOCK (1 << 0) #define NB_CFG_MSR 0xC001001f #define FidVidStatus 0xC0010042 +#define MC0_CTL_MASK 0xC0010044 #define MC1_CTL_MASK 0xC0010045 #define MC4_CTL_MASK 0xC0010048 #define MSR_INTPEND 0xC0010055 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 51ef2e0..b882e2f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -83,7 +83,6 @@ #define IA32_VMX_BASIC_MSR 0x480 #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define IA32_VMX_MISC_MSR 0x485 -#define MC0_CTL_MASK 0xC0010044 #define IA32_PM_ENABLE 0x770 #define IA32_HWP_CAPABILITIES 0x771 diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index e0c2791..598bfb5 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/reset.h> +#include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <acpi/acpi.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/56246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Gerrit-Change-Number: 56246 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/mca: use mca_clear_status()
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56260 ) Change subject: soc/amd/picasso/mca: use mca_clear_status() ...................................................................... soc/amd/picasso/mca: use mca_clear_status() Since we can use both the old MCA registers and the new MCAX registers to access the MCA status registers, we can use the common mca_clear_status function here. Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56260 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/mca.c 1 file changed, 3 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 973b3b5..23d7b61 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -181,19 +181,11 @@ } } -static void mca_clear_errors(void) -{ - const unsigned int num_banks = mca_get_bank_count(); - const msr_t msr = {.lo = 0, .hi = 0}; - - /* Zero all machine check error status registers */ - for (unsigned int i = 0 ; i < num_banks ; i++) - wrmsr(MCAX_STATUS_MSR(i), msr); -} - /* Check the Machine Check Architecture Extension registers */ void check_mca(void) { mca_check_all_banks(); - mca_clear_errors(); + /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are + aliases, we can use either set of registers. */ + mca_clear_status(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26 Gerrit-Change-Number: 56260 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021