coreboot-gerrit July 2021

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Nikolai Vyssotski (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Michał Żygowski, Marshall Dawson, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Marshall Dawson, Subrata Banik, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56190 to look at the new patch set (#5). Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... src/drivers/intel/fsp2_0: allow larger FSP 2.0 header This is in preparation for migrating EDK2 to more recent version(s). In EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0 header (FspMultiPhaseSiInitEntryOffset). This increases the length of the header from 72 to 76. Instead of checking for exact length check reported header length against known minimum length for a given FSP version. BUG=b:180186886 TEST=build/boot with both header flavors Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 --- M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/util.c 2 files changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/56190/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs
by Subrata Banik (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56298 ) Change subject: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56298/comment/fb27e142_f3bcb3b7 PS2, Line 308: m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); : m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; > I find it confusing, and wouldn't fit in one line anyway https://stackoverflow.com/questions/19353686/multiple-assignment-in-one-line 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/56298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80 Gerrit-Change-Number: 56298 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:30:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs
by Angel Pons (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56298 ) Change subject: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56298/comment/0fbfc77d_9dd64b8f PS2, Line 308: m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); : m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; > Just curious, any opinions on this style? […] I find it confusing, and wouldn't fit in one line anyway -- To view, visit https://review.coreboot.org/c/coreboot/+/56298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80 Gerrit-Change-Number: 56298 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:27:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add Star Labs labtop series
by Sean Rhodes (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56088 to look at the new patch set (#29). Change subject: mainboard: Add Star Labs labtop series ...................................................................... mainboard: Add Star Labs labtop series Add support for: LabTop Mk III (kbl-r) LabTop Mk IV (cml) StarBook Mk V (tgl) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 --- M Documentation/distributions.md M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/labtop.md M MAINTAINERS A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/devtree.c A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/gpio.c A src/mainboard/starlabs/labtop/variants/cml/hda_verb.c A src/mainboard/starlabs/labtop/variants/cml/include/variant/ec.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/devtree.c A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/gpio.c A src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c A src/mainboard/starlabs/labtop/variants/kbl/include/variant/ec.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.c A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.c A src/mainboard/starlabs/labtop/variants/kbl/romstage.c A src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc A src/mainboard/starlabs/labtop/variants/tgl/board.fmd A src/mainboard/starlabs/labtop/variants/tgl/data.vbt A src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb A src/mainboard/starlabs/labtop/variants/tgl/devtree.c A src/mainboard/starlabs/labtop/variants/tgl/gpio.c A src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c A src/mainboard/starlabs/labtop/variants/tgl/include/variant/ec.h A src/mainboard/starlabs/labtop/variants/tgl/romstage.c 61 files changed, 3,295 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56088/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/56088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Gerrit-Change-Number: 56088 Gerrit-PatchSet: 29 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs
by Tim Wawrzynczak (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56298 ) Change subject: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56298/comment/542c2ff6_8be8e86d PS2, Line 308: m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); : m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; Just curious, any opinions on this style? ``` m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/56298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80 Gerrit-Change-Number: 56298 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:25:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add TCSS USB device for ADL-M RVP
by Tim Wawrzynczak (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Bora Guvendik, Shaunak Saha, John Zhao, Bernardo Perez Priego, Sanrio Alvares, Deepti Deshatty, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55362 ) Change subject: mb/intel/adlrvp: Add TCSS USB device for ADL-M RVP ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > The purpose of this patch was to complement mechanism to set UPD 'UsbTcPortEn', this has already bee […] Doesn't seem necessary now -- To view, visit https://review.coreboot.org/c/coreboot/+/55362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058b789a9169d48af4e7d2314ed98e8f7884538f Gerrit-Change-Number: 55362 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sanrio Alvares <sanrio.alvares(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Sanrio Alvares <sanrio.alvares(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/cpu/mca: move function prototypes to local header
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56309 ) Change subject: soc/amd/common/block/cpu/mca: move function prototypes to local header ...................................................................... soc/amd/common/block/cpu/mca: move function prototypes to local header Since those functions are implemented and used only inside the common MCA(X) code, there's no need to have them in the header file that gets included in the SoC-specific code. Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/mca/mca.c M src/soc/amd/common/block/cpu/mca/mca_common.c M src/soc/amd/common/block/cpu/mca/mca_common_defs.h M src/soc/amd/common/block/cpu/mca/mcax.c M src/soc/amd/common/block/include/amdblocks/mca.h 5 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/56309/1 diff --git a/src/soc/amd/common/block/cpu/mca/mca.c b/src/soc/amd/common/block/cpu/mca/mca.c index c7d3e6f..2d91894 100644 --- a/src/soc/amd/common/block/cpu/mca/mca.c +++ b/src/soc/amd/common/block/cpu/mca/mca.c @@ -7,6 +7,7 @@ #include <cpu/x86/msr.h> #include <console/console.h> #include <types.h> +#include "mca_common_defs.h" static void mca_print_error(unsigned int bank) { diff --git a/src/soc/amd/common/block/cpu/mca/mca_common.c b/src/soc/amd/common/block/cpu/mca/mca_common.c index 0a37508..f029966 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_common.c +++ b/src/soc/amd/common/block/cpu/mca/mca_common.c @@ -2,6 +2,7 @@ #include <amdblocks/mca.h> #include <cpu/x86/msr.h> +#include "mca_common_defs.h" void check_mca(void) { diff --git a/src/soc/amd/common/block/cpu/mca/mca_common_defs.h b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h index 41d73d8..8142371 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_common_defs.h +++ b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h @@ -6,6 +6,8 @@ #include <amdblocks/mca.h> #include <cper.h> +void mca_check_all_banks(void); +void build_bert_mca_error(struct mca_bank_status *mci); enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci); void fill_generic_section(cper_proc_generic_error_section_t *sec, struct mca_bank_status *mci); diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c index cb01e1d..fecac0a 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax.c +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -6,6 +6,7 @@ #include <cpu/x86/msr.h> #include <console/console.h> #include <types.h> +#include "mca_common_defs.h" static void mca_print_error(unsigned int bank) { diff --git a/src/soc/amd/common/block/include/amdblocks/mca.h b/src/soc/amd/common/block/include/amdblocks/mca.h index 70a83ab..c84f232 100644 --- a/src/soc/amd/common/block/include/amdblocks/mca.h +++ b/src/soc/amd/common/block/include/amdblocks/mca.h @@ -12,8 +12,6 @@ }; void check_mca(void); -void mca_check_all_banks(void); -void build_bert_mca_error(struct mca_bank_status *mci); bool mca_has_expected_bank_count(void); bool mca_is_valid_bank(unsigned int bank); const char *mca_get_bank_name(unsigned int bank); -- To view, visit https://review.coreboot.org/c/coreboot/+/56309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d Gerrit-Change-Number: 56309 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/mca: factor out common MCA/MCAX check & print functionality
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56290 to look at the new patch set (#3). Change subject: soc/amd/*/mca: factor out common MCA/MCAX check & print functionality ...................................................................... soc/amd/*/mca: factor out common MCA/MCAX check & print functionality For Cezanne stubs are added for the functions that the SoC-specific code needs to provide. Since the mca_is_valid_bank stub on Cezanne always returns false, the checks get skipped for it at the moment. The actual functionality will be added in a later patch. Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/mca.c M src/soc/amd/common/block/cpu/mca/Makefile.inc A src/soc/amd/common/block/cpu/mca/mca.c A src/soc/amd/common/block/cpu/mca/mcax.c M src/soc/amd/common/block/include/amdblocks/mca.h M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 7 files changed, 132 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/56290/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Gerrit-Change-Number: 56290 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table
by Tim Wawrzynczak (Code Review) 14 Jul '21

14 Jul '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56175 ) Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > I believe I checked TGL and it enters S0ix just fine still, need to verify CML though. Verified S0ix still works on delbin (TGL) and dratini (CML) with the original patches. -- To view, visit https://review.coreboot.org/c/coreboot/+/56175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Gerrit-Change-Number: 56175 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 15:03:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: add BASEBOARD_DIR to support different baseboard
by Zhuohao Lee (Code Review) 14 Jul '21

14 Jul '21

Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56308 ) Change subject: mb/google/brya: add BASEBOARD_DIR to support different baseboard ...................................................................... mb/google/brya: add BASEBOARD_DIR to support different baseboard In order to support different baseboard configuration, we add the BASEBOARD_DIR to switch the directory. The expected structure looks like: mb ..|_ google .........|_ brya .............. |_ variants .....................|_ baseboard ..............................|_ brya ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ..............................|_ brask ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ......................|_ brya_variant1 ......................|_ brya_variant2 ......................|_ ... ......................|_ brask_variant1 ......................|_ brask_variant2 ......................|_ ... ...............|_ <all mb common code> BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Makefile.inc R src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc R src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb R src/mainboard/google/brya/variants/baseboard/brya/gpio.c R src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h R src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/gpio.h R src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/variants.h R src/mainboard/google/brya/variants/baseboard/brya/memory.c 9 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/56308/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 58635e9..3973004 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -38,6 +38,10 @@ def_bool n select SYSTEM_TYPE_LAPTOP +config BASEBOARD_DIR + string + default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA + config CHROMEOS select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES @@ -46,7 +50,7 @@ config DEVICETREE string - default "variants/baseboard/devicetree.cb" + default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb" config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index 0686a30..717cf5f 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -10,11 +10,12 @@ ramstage-y += ec.c VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR)) -subdirs-y += variants/baseboard +subdirs-y += variants/baseboard/$(BASEBOARD_DIR) subdirs-y += variants/$(VARIANT_DIR) subdirs-y += variants/$(VARIANT_DIR)/memory subdirs-y += spd -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/brya/variants/baseboard/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc similarity index 100% rename from src/mainboard/google/brya/variants/baseboard/Makefile.inc rename to src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb similarity index 100% rename from src/mainboard/google/brya/variants/baseboard/devicetree.cb rename to src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c similarity index 100% rename from src/mainboard/google/brya/variants/baseboard/gpio.c rename to src/mainboard/google/brya/variants/baseboard/brya/gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h similarity index 100% rename from src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h rename to src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h rename to src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/gpio.h diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/variants.h similarity index 100% rename from src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h rename to src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/variants.h diff --git a/src/mainboard/google/brya/variants/baseboard/memory.c b/src/mainboard/google/brya/variants/baseboard/brya/memory.c similarity index 100% rename from src/mainboard/google/brya/variants/baseboard/memory.c rename to src/mainboard/google/brya/variants/baseboard/brya/memory.c -- To view, visit https://review.coreboot.org/c/coreboot/+/56308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Gerrit-Change-Number: 56308 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021