coreboot-gerrit July 2021

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Change in coreboot[master]: drivers/intel/gma: Support IGD Opregion 2.1
by Meera Ravindranath (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Nico Huber, Krishna Prabhakaran, Furquan Shaikh, Maulik V Vaghela, Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Krishna Prabhakaran, Furquan Shaikh, Maulik V Vaghela, Selma Bensaid, Tim Wawrzynczak, Angel Pons, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52758 to look at the new patch set (#28). Change subject: drivers/intel/gma: Support IGD Opregion 2.1 ...................................................................... drivers/intel/gma: Support IGD Opregion 2.1 List of changes: 1. Define new configs for Opregion versions. 2. Assign RVDA to relative address of the Opregion buffer in case of opregion 2.1+. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b --- M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h 3 files changed, 37 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/52758/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/52758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b Gerrit-Change-Number: 52758 Gerrit-PatchSet: 28 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "mb/google/brya: Enable south XHCI ports 1 and 2"
by Sridhar Siricilla (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Tim Wawrzynczak, Ronak Kanabar. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56132 ) Change subject: Revert "mb/google/brya: Enable south XHCI ports 1 and 2" ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Gerrit-Change-Number: 56132 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 16 Jul 2021 03:51:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/collis: Fix pen ejection event
by Frank Chu (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Isaac Lee, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56331 ) Change subject: mb/google/volteer/variants/collis: Fix pen ejection event ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56331/comment/d8eca2b1_1f5506a7 PS2, Line 2: FrankChu > Yes, this is my account Done https://review.coreboot.org/c/coreboot/+/56331/comment/8d8dd2f2_03f3d878 PS2, Line 15: FrankChu > Yes, this is my account Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida5e5b35464471a7896cef392e178a3d2c0ea1aa Gerrit-Change-Number: 56331 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 16 Jul 2021 02:39:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG
by Dtrain Hsu (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Ian Feng, Henry Sun, Paul Menzel, Shou-Chieh Hsu, Karthik Ramasubramanian. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56248 ) Change subject: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/dedede/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56248/comment/7fb80871_2176463d PS4, Line 13: field TOUCHSCREEN 5 : option TOUCHSCREEN_ABSENT 0 : option TOUCHSCREEN_PRESENT 1 : end > Does this FW config field apply to the entire Dedede design or does it apply only to Cret? Yes, the fw_config field apply to entrire dedede design. That is origianl design. https://chrome-internal-review.googlesource.com/c/chromeos/program/dedede/+… -- To view, visit https://review.coreboot.org/c/coreboot/+/56248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b Gerrit-Change-Number: 56248 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 16 Jul 2021 02:07:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: add dram part id
by Malik Hsu (Code Review) 16 Jul '21

16 Jul '21

Malik Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56366 ) Change subject: mb/google/brya/variants/primus: add dram part id ...................................................................... mb/google/brya/variants/primus: add dram part id This change adds mem_parts_uesd.txt that contains the new memory parts used by primus and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:193813079 Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff --- M src/mainboard/google/brya/variants/primus/memory/Makefile.inc M src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt 3 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/56366/1 diff --git a/src/mainboard/google/brya/variants/primus/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc index 34944e3..c69c157 100644 --- a/src/mainboard/google/brya/variants/primus/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc @@ -2,6 +2,6 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B SPD_SOURCES += lp4x-spd-2.hex # ID = 1(0b0001) Parts = H9HCNNNFAMMLXR-NEE -SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt index 2166331..3f07783 100644 --- a/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt @@ -3,3 +3,6 @@ H9HCNNNFAMMLXR-NEE 1 (0001) H9HCNNNCPMMLXR-NEE 2 (0010) K4U6E3S4AA-MGCR 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt index 95bc596..bb14464 100644 --- a/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt @@ -2,3 +2,6 @@ H9HCNNNFAMMLXR-NEE H9HCNNNCPMMLXR-NEE K4U6E3S4AA-MGCR +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/56366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff Gerrit-Change-Number: 56366 Gerrit-PatchSet: 1 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] src/mb/adlrvp_m: Set SAGV to Auto
by Anil Kumar K (Code Review) 16 Jul '21

16 Jul '21

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56365 ) Change subject: [TEST] src/mb/adlrvp_m: Set SAGV to Auto ...................................................................... [TEST] src/mb/adlrvp_m: Set SAGV to Auto Change-Id: Ib064eb63c50b2e03ee845498126a0b521bd99568 --- M src/mainboard/intel/adlrvp/devicetree_m.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/56365/1 diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 34aee72..c1070ad 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -90,6 +90,7 @@ register "TcssAuxOri" = "0" register "s0ix_enable" = "1" + register "SaGv" = "SaGv_Enabled" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/56365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib064eb63c50b2e03ee845498126a0b521bd99568 Gerrit-Change-Number: 56365 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] src/mb/adlrvp_m: Enable SAGV FixedPoint 0
by Anil Kumar K (Code Review) 16 Jul '21

16 Jul '21

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56364 ) Change subject: [TEST] src/mb/adlrvp_m: Enable SAGV FixedPoint 0 ...................................................................... [TEST] src/mb/adlrvp_m: Enable SAGV FixedPoint 0 Change-Id: Iae836fdc77d3be1daefe7cbc15ea363fd5996cd6 --- M src/mainboard/intel/adlrvp/devicetree_m.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/56364/1 diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 34aee72..00df1eb 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -90,6 +90,7 @@ register "TcssAuxOri" = "0" register "s0ix_enable" = "1" + register "SaGv" = "SaGv_FixedPoint0" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/56364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae836fdc77d3be1daefe7cbc15ea363fd5996cd6 Gerrit-Change-Number: 56364 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
by Julius Werner (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56232 ) Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/common/block/apob/apob_cache.c: https://review.coreboot.org/c/coreboot/+/56232/comment/e2762f81_49d20e4f PS6, Line 71: if (fmap_locate_area(DEFAULT_MRC_CACHE, r) < 0) { > The RW boot device doesn't have the SPI DMA functionality. […] Oh, okay. You can use incoherent_rdev_init() to build a wrapper device that merges different read and write paths. Or just add a boot_device_rw() definition with the normal (non-DMA) write function to your spi_dma_rdev. Or just call the FMAP code twice. -- To view, visit https://review.coreboot.org/c/coreboot/+/56232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 Gerrit-Change-Number: 56232 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 16 Jul 2021 00:16:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by Felix Held (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Julius Werner, Eric Peers, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 ) Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/common/block/lpc/Kconfig: https://review.coreboot.org/c/coreboot/+/56228/comment/b705eb56_3b0224f0 PS6, Line 15: The SPI DMA controller : is only functional on Cezanne, Renoir or later SoCs. > I think checking a handful of specific AMD SoCs in AMD common code should be fine. […] ok, checking that it's not stoneyridge or picasso is probably the better solution then and since those are the oldest soc in soc/amd and i don't expect anything older getting added to soc/amd, this probably won't cause any problem in the future. let's use the depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE way then -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 16 Jul 2021 00:13:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: x86/smp/spinlock: Disable thread coop when taking spinlock
by Julius Werner (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56320 ) Change subject: x86/smp/spinlock: Disable thread coop when taking spinlock ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b929070b7f175965d4f37be693462fef26be052 Gerrit-Change-Number: 56320 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 16 Jul 2021 00:12:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2021