coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/common/pm: Introduce pm_fill_chipset_state
by Karthik Ramasubramanian (Code Review) 16 Jul '21

16 Jul '21

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Change in coreboot[master]: soc/amd/common/block/acpi: Extract event logging helpers
by Karthik Ramasubramanian (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56360 ) Change subject: soc/amd/common/block/acpi: Extract event logging helpers ...................................................................... soc/amd/common/block/acpi: Extract event logging helpers Move the event logging helpers defined in acpi into a separate library. This will allow logging power management and GPE events for both S3 and Modern Standby. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/acpi/acpi.c A src/soc/amd/common/block/elog/Kconfig A src/soc/amd/common/block/elog/Makefile.inc A src/soc/amd/common/block/elog/elog.c A src/soc/amd/common/block/include/amdblocks/elog.h M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig 8 files changed, 64 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/56360/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 71cca6a..b917964 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -44,6 +44,7 @@ select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_ELOG select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index df5b40d..d9807eb 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/acpimmio.h> -#include <amdblocks/acpi.h> #include <acpi/acpi.h> #include <acpi/acpi_pm.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/acpi.h> +#include <amdblocks/elog.h> #include <bootmode.h> #include <console/console.h> -#include <elog.h> #include <halt.h> #include <security/vboot/vboot_common.h> #include <soc/southbridge.h> @@ -65,36 +65,6 @@ return pm1_sts; } -static void log_pm1_status(uint16_t pm1_sts) -{ - if (!CONFIG(ELOG)) - return; - - if (pm1_sts & WAK_STS) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); - - if (pm1_sts & PWRBTN_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - - if (pm1_sts & RTC_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - - if (pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); -} - -static void log_gpe_events(const struct acpi_pm_gpe_state *state) -{ - int i; - uint32_t valid_gpe = state->gpe0_sts & state->gpe0_en; - - for (i = 0; i <= 31; i++) { - if (valid_gpe & (1U << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); - } -} - void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state) { state->pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); @@ -114,9 +84,9 @@ return; state = &ps->gpe_state; - log_pm1_status(state->pm1_sts); + elog_pm1_status(state->pm1_sts); print_pm1_status(state->pm1_sts); - log_gpe_events(state); + elog_gpe_events(state); } void acpi_clear_pm_gpe_status(void) diff --git a/src/soc/amd/common/block/elog/Kconfig b/src/soc/amd/common/block/elog/Kconfig new file mode 100644 index 0000000..f3b5ba3 --- /dev/null +++ b/src/soc/amd/common/block/elog/Kconfig @@ -0,0 +1,4 @@ +config SOC_AMD_COMMON_BLOCK_ELOG + bool + help + Select this option to use common event logging library for AMD SoC. diff --git a/src/soc/amd/common/block/elog/Makefile.inc b/src/soc/amd/common/block/elog/Makefile.inc new file mode 100644 index 0000000..bfcd704 --- /dev/null +++ b/src/soc/amd/common/block/elog/Makefile.inc @@ -0,0 +1,2 @@ +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_ELOG) += elog.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ELOG) += elog.c diff --git a/src/soc/amd/common/block/elog/elog.c b/src/soc/amd/common/block/elog/elog.c new file mode 100644 index 0000000..a8c2e44 --- /dev/null +++ b/src/soc/amd/common/block/elog/elog.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/elog.h> +#include <elog.h> +#include <soc/southbridge.h> + +void elog_pm1_status(uint16_t pm1_sts) +{ + if (!CONFIG(ELOG)) + return; + + if (pm1_sts & WAK_STS) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, + acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); + + if (pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + if (pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + if (pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); +} + +void elog_gpe_events(const struct acpi_pm_gpe_state *state) +{ + int i; + uint32_t valid_gpe = state->gpe0_sts & state->gpe0_en; + + if (!CONFIG(ELOG)) + return; + + for (i = 0; i <= 31; i++) { + if (valid_gpe & (1U << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); + } +} diff --git a/src/soc/amd/common/block/include/amdblocks/elog.h b/src/soc/amd/common/block/include/amdblocks/elog.h new file mode 100644 index 0000000..8b1e8fa --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/elog.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_AMD_COMMON_BLOCK_ELOG_H +#define SOC_AMD_COMMON_BLOCK_ELOG_H + +#include <amdblocks/acpi.h> + +void elog_pm1_status(uint16_t pm1_sts); + +void elog_gpe_events(const struct acpi_pm_gpe_state *state); + +#endif /* SOC_AMD_COMMON_BLOCK_ELOG_H */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 88bff50..c43ab6b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -35,6 +35,7 @@ select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_ELOG select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HDA diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index e799ea0..abafe3d 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -29,6 +29,7 @@ select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CAR + select SOC_AMD_COMMON_BLOCK_ELOG select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU -- To view, visit https://review.coreboot.org/c/coreboot/+/56360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba Gerrit-Change-Number: 56360 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Rename fill_chipset_state as pm_cache_chipset_state
by Karthik Ramasubramanian (Code Review) 16 Jul '21

16 Jul '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56359 ) Change subject: soc/amd: Rename fill_chipset_state as pm_cache_chipset_state ...................................................................... soc/amd: Rename fill_chipset_state as pm_cache_chipset_state Chipset power state is cached before any FSP call and later is added to CBMEM. Rename the function to match its purpose so that the fill operation can be added later to log any modern standby wake source. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I67b302227d79bacc5300f31b9428c66cc530c6bc Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/include/amdblocks/pmlib.h M src/soc/amd/common/block/pm/chipset_state.c M src/soc/amd/picasso/romstage.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56359/1 diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 9e863c3..37c2bcd 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -21,7 +21,7 @@ post_code(0x41); /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); + pm_cache_chipset_state(); fsp_memory_init(acpi_is_wakeup_s3()); diff --git a/src/soc/amd/common/block/include/amdblocks/pmlib.h b/src/soc/amd/common/block/include/amdblocks/pmlib.h index d9b80a2..fae48cb 100644 --- a/src/soc/amd/common/block/include/amdblocks/pmlib.h +++ b/src/soc/amd/common/block/include/amdblocks/pmlib.h @@ -18,6 +18,6 @@ void pm_set_power_failure_state(void); /* stash ACPI PM/GPE and GPIO wake state before FSP-M call */ -void fill_chipset_state(void); +void pm_cache_chipset_state(void); #endif /* SOC_AMD_COMMON_BLOCK_PMLIB_H */ diff --git a/src/soc/amd/common/block/pm/chipset_state.c b/src/soc/amd/common/block/pm/chipset_state.c index 3a4a0ba..abe64d7 100644 --- a/src/soc/amd/common/block/pm/chipset_state.c +++ b/src/soc/amd/common/block/pm/chipset_state.c @@ -8,7 +8,7 @@ static struct chipset_power_state chipset_state; -void fill_chipset_state(void) +void pm_cache_chipset_state(void) { acpi_fill_pm_gpe_state(&chipset_state.gpe_state); gpio_fill_wake_state(&chipset_state.gpio_state); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 1972410..e702649 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -22,7 +22,7 @@ post_code(0x42); /* Snapshot chipset state prior to any FSP call. */ - fill_chipset_state(); + pm_cache_chipset_state(); post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3()); -- To view, visit https://review.coreboot.org/c/coreboot/+/56359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b302227d79bacc5300f31b9428c66cc530c6bc Gerrit-Change-Number: 56359 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot/secdata_tpm: Add WRITE_STCLEAR attr to kernel ARB space
by Aseda Aboagye (Code Review) 16 Jul '21

16 Jul '21

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56358 ) Change subject: vboot/secdata_tpm: Add WRITE_STCLEAR attr to kernel ARB space ...................................................................... vboot/secdata_tpm: Add WRITE_STCLEAR attr to kernel ARB space This commit adds the WRITE_STCLEAR TPM attribute to the kernel antirollback space. When an STCLEAR attribute is set, this indicates that the TPM object will need to be reloaded after any TPM Startup(CLEAR). This is useful for protecting the kernel antirollback space from being written to by the OS via the WriteLock command, and allowing platformHierarchy to remain enabled if desired. One use case could be to update the TPM firmware without having to clear the owner. BUG=b:186029006 BRANCH=None TEST=Build and flash a chromebook with no kernel antirollback space set up, boot to chrome OS, run `tpm_manager_client get_space_info --index=0x1007` and verify that the WRITE_STCLEAR attribute is present. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I3181b4c18acd908e924ad858b677e891312423fe --- M src/security/vboot/secdata_tpm.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/56358/1 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index bedead7..2e3ec69 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -109,6 +109,14 @@ .TPMA_NV_PLATFORMCREATE = 1, }; +static const TPMA_NV kernel_space_attributes = { + .TPMA_NV_PPWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_WRITE_STCLEAR = 1, +}; + static const TPMA_NV fwmp_attr = { .TPMA_NV_PLATFORMCREATE = 1, .TPMA_NV_OWNERWRITE = 1, @@ -247,7 +255,7 @@ uint32_t kernel_space_size = vb2api_secdata_kernel_create(ctx); return setup_space("kernel", KERNEL_NV_INDEX, ctx->secdata_kernel, - kernel_space_size, rw_space_attributes, NULL, 0); + kernel_space_size, kernel_space_attributes, NULL, 0); } static uint32_t set_mrc_hash_space(uint32_t index, const uint8_t *data) -- To view, visit https://review.coreboot.org/c/coreboot/+/56358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3181b4c18acd908e924ad858b677e891312423fe Gerrit-Change-Number: 56358 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by build bot (Jenkins) (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Julius Werner, Eric Peers, Karthik Ramasubramanian, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 ) Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/common/block/lpc/spi_dma.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124345): https://review.coreboot.org/c/coreboot/+/56228/comment/ad14e7b6_43045bf5 PS7, Line 71: * it easier to debug why the SPI DMA wasn't used. 'wasn' may be misspelled - perhaps 'was'? -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jul 2021 23:37:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/thread: Rename thread_cooperate and thread_prevent_coop
by Raul Rangel (Code Review) 16 Jul '21

16 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56357 ) Change subject: lib/thread: Rename thread_cooperate and thread_prevent_coop ...................................................................... lib/thread: Rename thread_cooperate and thread_prevent_coop Renaming them to thread_coop_disable()/thread_coop_enable() makes them sound like a pair. BUG=b:179699789 TEST=Boot guybrush to OS Suggested-by: Julius Werner <jwerner(a)chromium.org> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1d70c18965f53e733e871ca03107270612efa4fc --- M src/include/thread.h M src/lib/thread.c 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/56357/1 diff --git a/src/include/thread.h b/src/include/thread.h index 8f12343..ee1e277 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -50,8 +50,8 @@ * not occur. The critical sections can be nested. Just make sure the methods * are used in pairs. */ -void thread_cooperate(void); -void thread_prevent_coop(void); +void thread_coop_enable(void); +void thread_coop_disable(void); static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { @@ -81,8 +81,8 @@ { return -1; } -static inline void thread_cooperate(void) {} -static inline void thread_prevent_coop(void) {} +static inline void thread_coop_enable(void) {} +static inline void thread_coop_disable(void) {} struct cpu_info; static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } #endif diff --git a/src/lib/thread.c b/src/lib/thread.c index 266ea38..47a23ac 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -114,7 +114,7 @@ static void idle_thread(void *unused) { /* This thread never voluntarily yields. */ - thread_prevent_coop(); + thread_coop_disable(); while (1) timers_run(); } @@ -352,7 +352,7 @@ return 0; } -void thread_cooperate(void) +void thread_coop_enable(void) { struct thread *current; @@ -366,7 +366,7 @@ current->can_yield++; } -void thread_prevent_coop(void) +void thread_coop_disable(void) { struct thread *current; -- To view, visit https://review.coreboot.org/c/coreboot/+/56357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d70c18965f53e733e871ca03107270612efa4fc Gerrit-Change-Number: 56357 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/thread: Clean up initialization sequence
by Raul Rangel (Code Review) 16 Jul '21

16 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56356 ) Change subject: lib/thread: Clean up initialization sequence ...................................................................... lib/thread: Clean up initialization sequence idle_thread_init was actually configuring the BSP thread at the end. We can instead do this in threads_initialize. This now lets us set initialized after the idle thread has been setup. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I7f1d6afac3b0622612565b37c61fbd2cd2481552 --- M src/lib/thread.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/56356/1 diff --git a/src/lib/thread.c b/src/lib/thread.c index a8c0772c..d44c218 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -213,8 +213,6 @@ /* Queue idle thread to run once all other threads have yielded. */ prepare_thread(t, idle_thread, NULL, call_wrapper, NULL); push_runnable(t); - /* Mark the currently executing thread to cooperate. */ - thread_cooperate(); } /* Don't inline this function so the timeout_callback won't have its storage @@ -260,6 +258,7 @@ ci->thread = t; t->stack_orig = (uintptr_t)ci; t->id = 0; + t->can_yield = 1; stack_top = &thread_stacks[CONFIG_STACK_SIZE] - sizeof(struct cpu_info); for (i = 1; i < TOTAL_NUM_THREADS; i++) { @@ -270,9 +269,9 @@ free_thread(t); } - initialized = 1; - idle_thread_init(); + + initialized = 1; } int thread_run(void (*func)(void *), void *arg) -- To view, visit https://review.coreboot.org/c/coreboot/+/56356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f1d6afac3b0622612565b37c61fbd2cd2481552 Gerrit-Change-Number: 56356 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
by Raul Rangel (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Julius Werner, Eric Peers, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56232 to look at the new patch set (#8). Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV ...................................................................... soc/amd/common/apob: Add support for asynchronously reading APOB_NV This CL adds a method that can start the processes of reading the APOB from SPI. It does require more RAM in ramstage since we no longer mmap the buffer in the happy path. This will allow us to reduce our boot time by ~10ms. The SoC code will need to be updated to call start_apob_cache_read at a point where it makes sense. BUG=b:179699789 TEST=With this and the patches above I can see a 10 ms reduction in boot time on guybrush. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 --- M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/include/amdblocks/apob_cache.h 2 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56232/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 Gerrit-Change-Number: 56232 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/thread: Add mutex
by Raul Rangel (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Raul Rangel, Eric Peers, Felix Held. Hello build bot (Jenkins), Julius Werner, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56230 to look at the new patch set (#7). Change subject: lib/thread: Add mutex ...................................................................... lib/thread: Add mutex We need a way to protect shared resources. Since we are using cooperative multitasking the mutex implementation is pretty trivial. The delays are implemented using a timer queue. So the task with the next expiration date will always be at the beginning of the queue. If a task (A) wishes to yield control to the next task (B) that is holding onto the mutex, without encountering a delay of its own (i.e., udelay(0)), then we need to ensure the next task (B) is at the head of the queue. We do this by using a `0 us` delay in mutex_lock. If we were to use anything larger than a `0 us` delay, a `udelay(0)` by the task (A) that just unlocked the mutex will most likely not schedule the next task (B) that was holding onto the mutex. BUG=b:179699789 TEST=Verify thread lock and unlock. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff --- M src/include/thread.h M src/lib/thread.c 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/56230/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff Gerrit-Change-Number: 56230 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: x86/smp/spinlock: Disable thread coop when taking spinlock
by Raul Rangel (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56320 to look at the new patch set (#3). Change subject: x86/smp/spinlock: Disable thread coop when taking spinlock ...................................................................... x86/smp/spinlock: Disable thread coop when taking spinlock Switching threads while holding a spinlock can lead to a deadlock. This happens if you have two thread trying to print to the serial console because the uart code uses udelay. BUG=b:179699789 TEST=Boot guybrush and no longer see a deadlock when printing to console from a second thread. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1b929070b7f175965d4f37be693462fef26be052 --- M src/arch/x86/include/arch/smp/spinlock.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/56320/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b929070b7f175965d4f37be693462fef26be052 Gerrit-Change-Number: 56320 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021