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Change subject: lib/thread: Allow nesting thread_cooperate and thread_prevent_coop
......................................................................
Patch Set 2:
(4 comments)
File src/include/thread.h:
https://review.coreboot.org/c/coreboot/+/56350/comment/7c32798b_bbce09b6
PS1, Line 54: void thread_prevent_coop(void);
> While we're here, are we happy with the names for this? I feel like something that makes it a bit mo […]
Done
File src/lib/thread.c:
https://review.coreboot.org/c/coreboot/+/56350/comment/08d499f9_c44113c4
PS1, Line 217: thread_cooperate();
> I agree this doesn't belong here, but maybe it would be better to put it at the end of threads_initi […]
I think moving the `initialized = 1` after the `idle_thread_init` solves that problem. The reason it was before the `idle_thread_init` call was because then the BSP thread wouldn't have its `can_yield` set correctly with out it. I'll rework this.
https://review.coreboot.org/c/coreboot/+/56350/comment/c568c3a9_ac2d3eae
PS1, Line 34: return (t != NULL && t->can_yield > 0);
> This check is a bit odd since under normal use can_yield should either be 0 or negative. […]
Normally `can_yield` will be 1. It's setup by `prepare_thread`. I wanted to keep it so 1 means can_yield. 0 or negative means can't yield. This is why I kept the name. I can rework it if you feel strongly about it.
https://review.coreboot.org/c/coreboot/+/56350/comment/bb29a2bd_87bdc280
PS1, Line 363:
> Would be good to assert() that we were in a critical section when this is called.
Done
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Hello build bot (Jenkins), Furquan Shaikh, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56350
to look at the new patch set (#2).
Change subject: lib/thread: Allow nesting thread_cooperate and thread_prevent_coop
......................................................................
lib/thread: Allow nesting thread_cooperate and thread_prevent_coop
This change allows nesting critical sections, and frees the caller from
having to keep track of whether the thread has coop enabled.
BUG=b:179699789
TEST=Boot guybrush with SPI DMA
Suggested-by: Julius Werner <jwerner(a)chromium.org>
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I325ab6181b17c5c084ca1e2c181b4df235020557
---
M src/include/thread.h
M src/lib/thread.c
2 files changed, 18 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56350/2
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/block/lpc/Kconfig:
https://review.coreboot.org/c/coreboot/+/56228/comment/8e24cc1d_bcfd4d1d
PS6, Line 15: The SPI DMA controller
: is only functional on Cezanne, Renoir or later SoCs.
> > I guess I could do a `depends on !SOC_AMD_PICASSO and !SOC_AMD_STONEYRIDGE`. […]
Done
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/Kconfig
M src/soc/amd/common/block/lpc/spi_dma.c
3 files changed, 202 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56228/7
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/block/lpc/Kconfig:
https://review.coreboot.org/c/coreboot/+/56228/comment/8c7a8897_809a3b78
PS6, Line 15: The SPI DMA controller
: is only functional on Cezanne, Renoir or later SoCs.
> > I guess I could do a `depends on !SOC_AMD_PICASSO and !SOC_AMD_STONEYRIDGE`. […]
i'd like to avoid to have checks for specific socs in the common code. only selecting it form the socs that support this and having the info that it won't work on the older ones in the help text is imho a much cleaner and better solution
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56232 )
Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/56232/comment/226394b4_df2b5250
PS6, Line 71: if (fmap_locate_area(DEFAULT_MRC_CACHE, r) < 0) {
> I would say just use the RW rdev right away in that case, or just look up the FMAP section again. […]
The RW boot device doesn't have the SPI DMA functionality. I can throw up a CL to update get_apob_from_nv_region.
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/block/lpc/Kconfig:
https://review.coreboot.org/c/coreboot/+/56228/comment/5d253ff6_311d834d
PS6, Line 15: The SPI DMA controller
: is only functional on Cezanne, Renoir or later SoCs.
> I guess I could do a `depends on !SOC_AMD_PICASSO and !SOC_AMD_STONEYRIDGE`.
Right, I'd do it like that.
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Change subject: lib/prog_loaders: Add payload_preload
......................................................................
Patch Set 9: Code-Review+2
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Change subject: lib/prog_loaders: Add payload_preload
......................................................................
Patch Set 9:
(2 comments)
File src/lib/prog_loaders.c:
https://review.coreboot.org/c/coreboot/+/56051/comment/bc282502_3d0de06f
PS8, Line 160: return;
> I don't think we need a dead_code here. […]
Hmm... if you want callers to just always call this and have it figure itself out, maybe do the thing where there's a static inline stub in the header file when the option is disabled instead? I think that's a more common pattern for this in coreboot.
https://review.coreboot.org/c/coreboot/+/56051/comment/bedca5cc_d0c7ae1f
PS8, Line 162: if (prog_locate_hook(payload))
> Are you saying remove it from payload_preload and change payload_load to the following? […]
Yeah, I would say write it the way you did there. It's really more about blocking program execution than program loading. If you do it up here it might get confused from running way earlier than intended.
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Change subject: lib/thread: Move thread_run and thread_run_until outside of #if guard
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Ahh, here you did it already. Excellent! Ignore my comment in the earlier CL.
lol, yeah it's been interesting shuffling the patches around...
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