coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'
by Subrata Banik (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56369 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' ...................................................................... soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/bootblock/report_platform.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/56369/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d Gerrit-Change-Number: 56369 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/thread: Add thread_yield helper method
by Furquan Shaikh (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Raul Rangel. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56349 ) Change subject: lib/thread: Add thread_yield helper method ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b60c35b183cff6871d7ba70b36eb33b136c735 Gerrit-Change-Number: 56349 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 16 Jul 2021 06:30:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by Furquan Shaikh (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Eric Peers, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 ) Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... Patch Set 7: Code-Review+2 (4 comments) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/56228/comment/ec72759a_fe9b5a96 PS5, Line 134: if (spi_dma_has_error()) > Done. I didn't clear the error since we clear it before we start a new transaction. Ack. https://review.coreboot.org/c/coreboot/+/56228/comment/f0525772_145fd43c PS5, Line 173: udelay(10); > This is what I replied to Eric: […] Ack. https://review.coreboot.org/c/coreboot/+/56228/comment/7383316f_a2744501 PS5, Line 177: ); > Since we are yielding control for an unknown amount of time, there is no easy way to know how long t […] Ack. File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/56228/comment/986fdc9f_f73530c4 PS7, Line 101: We should have complete control over the DMA controller, so there shouldn't : * be any outstanding transactions. Based on the comment you added on line 230, can there ever be a scenario that PSP decides to use the SPI DMA for any purpose while x86 is booting up? Just wondering if this should be an assert or if it should be a busy-wait so that x86 can take control once PSP is done. -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 16 Jul 2021 06:29:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: add BASEBOARD_DIR to support different baseboard
by Furquan Shaikh (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Zhuohao Lee. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56308 ) Change subject: mb/google/brya: add BASEBOARD_DIR to support different baseboard ...................................................................... Patch Set 1: (4 comments) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/56308/comment/e8a4f142_d17a1037 PS1, Line 1: BOARD_GOOGLE_BASEBOARD_BRYA This will have to be updated to allow for different Kconfigs for different baseboards. Something like what zork does should work: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… * BOARD_GOOGLE_BASEBOARD_BRYA * BOARD_GOOGLE_BASEBOARD_BRASK Are you planning to push that as a separate change? https://review.coreboot.org/c/coreboot/+/56308/comment/1146d1c9_f8ae977c PS1, Line 37: config BASEBOARD_BRYA_LAPTOP : def_bool n : select SYSTEM_TYPE_LAPTOP There is some clean up required for this as well. I think SYSTEM_TYPE_LAPTOP should be selected for all BOARD_GOOGLE_BASEBOARD_BRYA at least for now. Maybe it can be pushed as a separate change. https://review.coreboot.org/c/coreboot/+/56308/comment/95242a1c_f00aa24a PS1, Line 46: CHROMEOS_DRAM_PART_NUMBER_IN_CBI I think this is specific to brya baseboard. If you are planning to handle all memory differences separately, feel free to push this along with that. https://review.coreboot.org/c/coreboot/+/56308/comment/a09f5473_9d8a0f31 PS1, Line 77: BOARD_GOOGLE_BRYA0 This will have to be changed to BOARD_GOOGLE_BASEBOARD_BRYA. Also the string should be Google_Brya. -- To view, visit https://review.coreboot.org/c/coreboot/+/56308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Gerrit-Change-Number: 56308 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Fri, 16 Jul 2021 05:58:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'
by Subrata Banik (Code Review) 16 Jul '21

16 Jul '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56369 ) Change subject: soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' ...................................................................... soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/bootblock/report_platform.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/56369/1 diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 03d65a4..e87c2b1 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -9,11 +9,11 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> +#include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <intelblocks/mp_init.h> #include <soc/bootblock.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index afbd747..4574720 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -13,7 +13,6 @@ #include <intelblocks/cse.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> -#include <intelblocks/mp_init.h> #include <intelblocks/pmclib.h> #include <intelblocks/tcss.h> #include <intelblocks/xdci.h> diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 15a11cd..44c6d84 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> -#include <intelblocks/mp_init.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> #include <soc/msr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/56369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d Gerrit-Change-Number: 56369 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1
by Furquan Shaikh (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Angel Pons, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56156 ) Change subject: soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a6f3df185003a4e38faa920f867ace0b97ab2b Gerrit-Change-Number: 56156 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 16 Jul 2021 05:52:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: Support IGD Opregion 2.1
by Furquan Shaikh (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Nico Huber, Krishna Prabhakaran, Maulik V Vaghela, Selma Bensaid, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52758 ) Change subject: drivers/intel/gma: Support IGD Opregion 2.1 ...................................................................... Patch Set 28: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b Gerrit-Change-Number: 52758 Gerrit-PatchSet: 28 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 16 Jul 2021 05:52:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Expose FIVR config to mainboard
by Lean Sheng Tan (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55861 ) Change subject: soc/intel/elkhartlake: Expose FIVR config to mainboard ...................................................................... Patch Set 4: (3 comments) File src/soc/intel/elkhartlake/chip.h: https://review.coreboot.org/c/coreboot/+/55861/comment/d70666df_e3dc60e9 PS3, Line 77: > I would align FIVR_VOLTAGE_MIN_RETENTION with FIVR_VOLTAGE_NORMAL as it belongs to the same bitmask. Done https://review.coreboot.org/c/coreboot/+/55861/comment/2c268eb6_86e2cb2c PS3, Line 382: enum fivr_states v1p05_state_bitmap; : enum fivr_states vnn_state_bitmap; : enum fivr_states vnn_sx_state_bitmap; : enum fivr_supported_voltage v1p05_volt_bitmap; : enum fivr_supported_voltage vnn_volt_bitmap; > Is there any benefit in calling all the members *_bitmap? The type is clear with the enum, so why no […] Done https://review.coreboot.org/c/coreboot/+/55861/comment/5a9dd731_7f63a8a4 PS3, Line 393: unsigned int vcc_low_high_usec; : /* From retention mode voltage to high current mode voltage */ : unsigned int vcc_ret_high_usec; : /* From retention mode voltage to low current mode voltage */ : unsigned int vcc_ret_low_usec; : /* From off(0V) to high current mode voltage */ : unsigned int vcc_off_high_usec; > It seems like "us" is more often used for µs along the tree than usec. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5 Gerrit-Change-Number: 55861 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 16 Jul 2021 05:49:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/ehlcrb: Update FIVR configs
by Lean Sheng Tan (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55981 to look at the new patch set (#3). Change subject: mb/intel/ehlcrb: Update FIVR configs ...................................................................... mb/intel/ehlcrb: Update FIVR configs This patch sets the optimized FIVR configs for ehlcrb customized based on the performance measurements to achieve the better power savings in sleep states. - Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5 states. - Update the supported voltage states. - Update max supported current, voltage transition time and RFI spread spectrum. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/55981/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b Gerrit-Change-Number: 55981 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Expose FIVR config to mainboard
by Lean Sheng Tan (Code Review) 16 Jul '21

16 Jul '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55861 to look at the new patch set (#4). Change subject: soc/intel/elkhartlake: Expose FIVR config to mainboard ...................................................................... soc/intel/elkhartlake: Expose FIVR config to mainboard Elkhart Lake provides option to configure FIVR (Fully Integrated Voltage Regulators) via parameters in FSP-S. This CL removes fixed FIVR config values and expose these parameters to the devicetree so that they can be configured on mainboard level as needed. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5 --- M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 75 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/55861/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5 Gerrit-Change-Number: 55861 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021