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Change subject: libpayload: Mark Intel 300 series AHCI as tested
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Patch Set 1: Code-Review+1
(1 comment)
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https://review.coreboot.org/c/coreboot/+/56666/comment/a8c78bd8_2efe724e
PS1, Line 8:
Tested on what device?
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Change subject: libpayload: Mark Intel 300 series AHCI as tested
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Patch Set 1: Code-Review+2
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Change subject: util/xcompile: Allow overriding default compiler path
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56643/comment/13d7c410_69efb4da
PS1, Line 17:
> Can you give an example, how this is set in Chromium OS?
CB:3057570: `export GENERIC_COMPILER_PREFIX="invalid"`
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Change subject: soc/intel/cannonlake: Unbreak some short lines
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/cannonlake: Report correct latencies for C states
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Patch Set 1:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/56664/comment/6d65e002_96c6da26
PS1, Line 8:
tested? if yes, how?
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Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 1:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/56662/comment/3c3330bb_d8169b33
PS1, Line 14:
How was this tested? Does S0ix still work?
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Change subject: soc/intel/alderlake: Disable Crashlog by default
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Patch Set 1: Code-Review-1
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IMO keeping crashlog is worth more than 5ms of boot time
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Change subject: mb/google/brya: Disable crashlog on brya
......................................................................
Patch Set 1: Code-Review-1
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We explicitly enabled crashlog for brya0 (the reference board) only to get access to more debug information, why disable it?
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