Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56674 )
Change subject: soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to table
......................................................................
soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to table
GPIO bank 3 isn't used in coreboot, but the existence is documented in
both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and
for those two SoCs all 4 banks are covered by the corresponding
Memory32Fixed region in the DSDT.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1
---
M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56674/1
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
index 176dc2b..ebfc039 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
@@ -72,6 +72,8 @@
* +---------------------------------------------------------------------------+
* |0x1700 GPIO configuration registers bank 2 (following bank 1) |
* +---------------------------------------------------------------------------+
+ * |0x1800 GPIO configuration registers bank 3 (following bank 2) |
+ * +---------------------------------------------------------------------------+
* |0x1c00 xHCI Power Management registers |
* +---------------------------------------------------------------------------+
* |0x1d00 Wake device (AC DC timer) |
--
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Gerrit-Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1
Gerrit-Change-Number: 56674
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
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Attention is currently required from: Furquan Shaikh, Angel Pons, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56617 )
Change subject: soc/intel/alderlake: Clear RTC_BATTERY_DEAD
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> Ideally good to split out individual SoC changes. […]
incoming
File src/soc/intel/alderlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/56617/comment/8c9aeb27_03d37726
PS1, Line 188: soc_get_rtc_failed
> `soc_get_rtc_failed()` gets called only in ramstage. […]
Find a patch at the end of the this train that re-initializes CMOS in this particular boot flow.
--
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Gerrit-Change-Id: I9dc21c19ea8ce561e9655e189ec26aba7a07967e
Gerrit-Change-Number: 56617
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56673 )
Change subject: security/vboot: Initialize CMOS before attempting backup
......................................................................
security/vboot: Initialize CMOS before attempting backup
On an x86 board, in the case of a persistent early recovery request,
where the RTC has failed, and the flash VBNV region is also invalid,
RTC_BATTERY_DEAD is cleared now (by earlier patchsets), so in this flow,
the CMOS will not get reinitialized. This patch fixes that by performing
the initialization in the vbnv_cmos driver.
BUG=b:181678769
Change-Id: I711457a3ed5c22ec51ebd5fe7f05400da17d1b11
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/security/vboot/vbnv_cmos.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56673/1
diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c
index 35e4c41..f1a13ef 100644
--- a/src/security/vboot/vbnv_cmos.c
+++ b/src/security/vboot/vbnv_cmos.c
@@ -71,9 +71,13 @@
{
/* If no CMOS failure just defer to the normal read path for checking
vbnv contents' integrity. */
- if (!vbnv_cmos_failed())
+ const int failed = vbnv_cmos_failed();
+ if (!failed)
return;
+ /* Re-initialize CMOS contents first */
+ cmos_init(failed);
+
/* In the case of CMOS failure force the backup. If backup wasn't used
force the vbnv CMOS to be reset. */
if (!restore_from_backup(vbnv_copy)) {
--
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Gerrit-Change-Number: 56673
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56672 )
Change subject: soc/intel/elkhartlake: Clear RTC_BATTERY_DEAD
......................................................................
soc/intel/elkhartlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty and RTC_BATTERY_DEAD
is set), if coreboot persistently requests recovery before FSP-M
finishes (which clears RTC_BATTERY_DEAD towards the end of its
execution), then vbnv_cmos_failed() will still return 1. Therefore,
immediately after reading (and returning 1 if set) RTC_BATTERY_DEAD, it
is cleared. This prevents an infinite boot loop when trying to set the
recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/elkhartlake/pmutil.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/56672/1
diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c
index ca82e16..9bd431d 100644
--- a/src/soc/intel/elkhartlake/pmutil.c
+++ b/src/soc/intel/elkhartlake/pmutil.c
@@ -178,6 +178,22 @@
return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
}
+static void clear_rtc_failed(void)
+{
+ clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
+}
+
+static int check_rtc_failed(uint32_t gen_pmcon_b)
+{
+ const int failed = rtc_failed(gen_pmcon_b);
+ if (failed) {
+ clear_rtc_failed();
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
+ }
+
+ return failed;
+}
+
int soc_get_rtc_failed(void)
{
const struct chipset_power_state *ps;
@@ -185,12 +201,12 @@
if (acpi_pm_state_for_rtc(&ps) < 0)
return 1;
- return rtc_failed(ps->gen_pmcon_b);
+ return check_rtc_failed(ps->gen_pmcon_b);
}
int vbnv_cmos_failed(void)
{
- return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+ return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
}
static inline int deep_s3_enabled(void)
--
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Gerrit-Change-Number: 56672
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Change subject: soc/intel/icelake: Clear RTC_BATTERY_DEAD
......................................................................
soc/intel/icelake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty and RTC_BATTERY_DEAD
is set), if coreboot persistently requests recovery before FSP-M
finishes (which clears RTC_BATTERY_DEAD towards the end of its
execution), then vbnv_cmos_failed() will still return 1. Therefore,
immediately after reading (and returning 1 if set) RTC_BATTERY_DEAD, it
is cleared. This prevents an infinite boot loop when trying to set the
recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I1a55df754c711b2afb8939b442019831c25cce29
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/icelake/pmutil.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56671/1
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 108b919..f552a8c 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -178,6 +178,22 @@
return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
}
+static void clear_rtc_failed(void)
+{
+ clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
+}
+
+static int check_rtc_failed(uint32_t gen_pmcon_b)
+{
+ const int failed = rtc_failed(gen_pmcon_b);
+ if (failed) {
+ clear_rtc_failed();
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
+ }
+
+ return failed;
+}
+
int soc_get_rtc_failed(void)
{
const struct chipset_power_state *ps;
@@ -185,12 +201,12 @@
if (acpi_pm_state_for_rtc(&ps) < 0)
return 1;
- return rtc_failed(ps->gen_pmcon_b);
+ return check_rtc_failed(ps->gen_pmcon_b);
}
int vbnv_cmos_failed(void)
{
- return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+ return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
}
static inline int deep_s3_enabled(void)
--
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Gerrit-Change-Id: I1a55df754c711b2afb8939b442019831c25cce29
Gerrit-Change-Number: 56671
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Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Change subject: soc/intel/jasperlake: Clear RTC_BATTERY_DEAD
......................................................................
soc/intel/jasperlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty and RTC_BATTERY_DEAD
is set), if coreboot persistently requests recovery before FSP-M
finishes (which clears RTC_BATTERY_DEAD towards the end of its
execution), then vbnv_cmos_failed() will still return 1. Therefore,
immediately after reading (and returning 1 if set) RTC_BATTERY_DEAD, it
is cleared. This prevents an infinite boot loop when trying to set the
recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/jasperlake/pmutil.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/56670/1
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c
index 4d9a123..d9ecb63 100644
--- a/src/soc/intel/jasperlake/pmutil.c
+++ b/src/soc/intel/jasperlake/pmutil.c
@@ -178,6 +178,22 @@
return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
}
+static void clear_rtc_failed(void)
+{
+ clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
+}
+
+static int check_rtc_failed(uint32_t gen_pmcon_b)
+{
+ const int failed = rtc_failed(gen_pmcon_b);
+ if (failed) {
+ clear_rtc_failed();
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
+ }
+
+ return failed;
+}
+
int soc_get_rtc_failed(void)
{
const struct chipset_power_state *ps;
@@ -185,12 +201,12 @@
if (acpi_pm_state_for_rtc(&ps) < 0)
return 1;
- return rtc_failed(ps->gen_pmcon_b);
+ return check_rtc_failed(ps->gen_pmcon_b);
}
int vbnv_cmos_failed(void)
{
- return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+ return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
}
static inline int deep_s3_enabled(void)
--
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Change subject: soc/intel/tigerlake: Clear RTC_BATTERY_DEAD
......................................................................
soc/intel/tigerlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty and RTC_BATTERY_DEAD
is set), if coreboot persistently requests recovery before FSP-M
finishes (which clears RTC_BATTERY_DEAD towards the end of its
execution), then vbnv_cmos_failed() will still return 1. Therefore,
immediately after reading (and returning 1 if set) RTC_BATTERY_DEAD, it
is cleared. This prevents an infinite boot loop when trying to set the
recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/tigerlake/pmutil.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/56669/1
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index c980a2c..aee2b3b 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -184,6 +184,22 @@
return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
}
+static void clear_rtc_failed(void)
+{
+ clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
+}
+
+static int check_rtc_failed(uint32_t gen_pmcon_b)
+{
+ const int failed = rtc_failed(gen_pmcon_b);
+ if (failed) {
+ clear_rtc_failed();
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
+ }
+
+ return failed;
+}
+
int soc_get_rtc_failed(void)
{
const struct chipset_power_state *ps;
@@ -191,12 +207,12 @@
if (acpi_pm_state_for_rtc(&ps) < 0)
return 1;
- return rtc_failed(ps->gen_pmcon_b);
+ return check_rtc_failed(ps->gen_pmcon_b);
}
int vbnv_cmos_failed(void)
{
- return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+ return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
}
static inline int deep_s3_enabled(void)
--
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Change subject: soc/intel/cannonlake: Clear RTC_BATTERY_DEAD
......................................................................
soc/intel/cannonlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty and RTC_BATTERY_DEAD
is set), if coreboot persistently requests recovery before FSP-M
finishes (which clears RTC_BATTERY_DEAD towards the end of its
execution), then vbnv_cmos_failed() will still return 1. Therefore,
immediately after reading (and returning 1 if set) RTC_BATTERY_DEAD, it
is cleared. This prevents an infinite boot loop when trying to set the
recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I54f519edb9f4295f83a581db9cb43f5ae5d0d483
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/cannonlake/pmutil.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/56668/1
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index a79d262..6baa926 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -178,6 +178,22 @@
return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
}
+static void clear_rtc_failed(void)
+{
+ clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
+}
+
+static int check_rtc_failed(uint32_t gen_pmcon_b)
+{
+ const int failed = rtc_failed(gen_pmcon_b);
+ if (failed) {
+ clear_rtc_failed();
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
+ }
+
+ return failed;
+}
+
int soc_get_rtc_failed(void)
{
const struct chipset_power_state *ps;
@@ -185,12 +201,12 @@
if (acpi_pm_state_for_rtc(&ps) < 0)
return 1;
- return rtc_failed(ps->gen_pmcon_b);
+ return check_rtc_failed(ps->gen_pmcon_b);
}
int vbnv_cmos_failed(void)
{
- return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+ return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
}
static inline int deep_s3_enabled(void)
--
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Hello build bot (Jenkins), Furquan Shaikh, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Clear RTC_BATTERY_DEAD
......................................................................
soc/intel/alderlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty and RTC_BATTERY_DEAD
is set), if coreboot persistently requests recovery before FSP-M
finishes (which clears RTC_BATTERY_DEAD towards the end of its
execution), then vbnv_cmos_failed() will still return 1. Therefore,
immediately after reading (and returning 1 if set) RTC_BATTERY_DEAD, it
is cleared. This prevents an infinite boot loop when trying to set the
recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I9dc21c19ea8ce561e9655e189ec26aba7a07967e
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/alderlake/pmutil.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56617/2
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56667 )
Change subject: guybrush: Document USB mapping in devicetree
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/56667/comment/2929332f_23a0a976
PS1, Line 167: },
Does USB3 ports not support USB A receptacle? Also same for WWAN, some WWAN use USB3 to support higher data rates - Are we not using any of those WWANs?
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