coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: drivers/intel/fsp2_0: Fix the FSP_T position
by Michał Żygowski (Code Review) 03 May '21

03 May '21

Attention is currently required from: Paul Menzel, Arthur Heymans, Andrey Petrov, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52850 ) Change subject: drivers/intel/fsp2_0: Fix the FSP_T position ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/52850/comment/0be637fb_d6eaab23 PS2, Line 81: The location for FSP-T. > > Maybe extend and explain, when this needs to be changed, and how the value can be determined? […] This value should be also set per SoC. It may differ across FSP releases. FSP-T is not relocated by CBFS IIRC, at least in my case it did not land at the address in CBFS specified in FSP header. -- To view, visit https://review.coreboot.org/c/coreboot/+/52850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Gerrit-Change-Number: 52850 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 May 2021 12:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
by Michał Żygowski (Code Review) 03 May '21

03 May '21

Attention is currently required from: Nico Huber, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52780 ) Change subject: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Very nice that you could fix it! […] Will try to split it, hopefully the "cosmetic" changes won't break anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/52780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia01c5e238d53f719bb0d15e106517b99432a0c31 Gerrit-Change-Number: 52780 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 03 May 2021 12:33:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/puff/var/dooly: enable touchscreen wakeup
by Edward O'Callaghan (Code Review) 03 May '21

03 May '21

Attention is currently required from: Sam McNally, Furquan Shaikh, Tony Huang, Tim Wawrzynczak, Keith Tzeng, Wisley Chen. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52725 ) Change subject: mb/google/puff/var/dooly: enable touchscreen wakeup ...................................................................... Patch Set 9: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52725/comment/8a1d92a2_01dbdfec PS9, Line 11: Add fake touchscreen enable_pin GPP_D9 to ensure meet power sequence T11 in spec v0.8. How? What is spec v0.8 can you elaborate with more detail here please? https://review.coreboot.org/c/coreboot/+/52725/comment/5f5bfa31_dac07b0d PS9, Line 13: empty pin when you say "empty" do you mean NC or do you mean GND plane? I assume you mean NC but I wanted to check? -- To view, visit https://review.coreboot.org/c/coreboot/+/52725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Gerrit-Change-Number: 52725 Gerrit-PatchSet: 9 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 May 2021 12:04:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Move the common part of SPI drivers to common/
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52854 ) Change subject: soc/mediatek: Move the common part of SPI drivers to common/ ...................................................................... soc/mediatek: Move the common part of SPI drivers to common/ The SPI drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Cherry P0 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe --- M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c M src/soc/mediatek/mt8192/include/soc/spi.h M src/soc/mediatek/mt8192/spi.c 8 files changed, 61 insertions(+), 148 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/52854/1 diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 918f3d2..a70b9b1 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -3,21 +3,12 @@ #ifndef MTK_COMMON_SPI_H #define MTK_COMMON_SPI_H +#include <device/mmio.h> #include <soc/gpio_base.h> #include <spi-generic.h> #include <types.h> enum { - SPI_CFG1_CS_IDLE_SHIFT = 0, - SPI_CFG1_PACKET_LOOP_SHIFT = 8, - SPI_CFG1_PACKET_LENGTH_SHIFT = 16, - - SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT, - SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT, - SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT, -}; - -enum { SPI_CMD_ACT_SHIFT = 0, SPI_CMD_RESUME_SHIFT = 1, SPI_CMD_RST_SHIFT = 2, @@ -59,7 +50,24 @@ SPI_PAD_SEL_MASK = 0x3 }; -struct mtk_spi_regs; +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); struct mtk_spi_bus { struct spi_slave slave; diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index afc64c6..f465027 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -34,6 +34,19 @@ return &spi_bus[slave->bus]; } +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, + u32 cs_ticks, unsigned int tick_dly) +{ + SET32_BITFIELDS(&regs->spi_cfg0_reg, SPI_CFG_CS_HOLD, cs_ticks - 1, + SPI_CFG_CS_SETUP, cs_ticks - 1); + + SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1, + SPI_CFG_SCK_HIGH, sck_ticks - 1); + + SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly, + SPI_CFG1_CS_IDLE, cs_ticks - 1); +} + static void spi_sw_reset(struct mtk_spi_regs *regs) { setbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); @@ -121,10 +134,8 @@ else size = MIN(*bytes_in, *bytes_out); - clrsetbits32(&regs->spi_cfg1_reg, - SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, - ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | - (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); + SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_PACKET_LENGTH, size - 1, + SPI_CFG1_PACKET_LOOP, 0); if (*bytes_out) { const uint8_t *outb = (const uint8_t *)out; diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index 47da0f8..b267aa0 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -7,32 +7,16 @@ #define SPI_BUS_NUMBER 1 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; -} mtk_spi_regs; +#define GET_SCK_REG(x) x->spi_cfg0_reg -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8) +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 23, 16) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 24) -enum { - SPI_CFG0_SCK_HIGH_SHIFT = 0, - SPI_CFG0_SCK_LOW_SHIFT = 8, - SPI_CFG0_CS_HOLD_SHIFT = 16, - SPI_CFG0_CS_SETUP_SHIFT = 24, -}; - -enum { - SPI_CFG1_TICK_DLY_SHIFT = 30, - SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT, -}; +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 4abd650..d3c8ad4 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -26,20 +26,6 @@ gpio_set_mode(GPIO(MSDC2_CMD), 0); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(&regs->spi_cfg0_reg, - ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | - SPI_CFG1_TICK_DLY_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 5efa618..5bc70e5 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -7,39 +7,18 @@ #define SPI_BUS_NUMBER 6 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; - uint32_t spi_cfg2_reg; - uint32_t spi_tx_src_64_reg; - uint32_t spi_rx_dst_64_reg; -} mtk_spi_regs; +#define GET_SCK_REG(x) x->spi_cfg2_reg -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) -enum { - SPI_CFG0_CS_HOLD_SHIFT = 0, - SPI_CFG0_CS_SETUP_SHIFT = 16, -}; +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) -enum { - SPI_CFG2_SCK_LOW_SHIFT = 0, - SPI_CFG2_SCK_HIGH_SHIFT = 16, -}; +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) -enum { - SPI_CFG1_TICK_DLY_SHIFT = 29, - SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, - -}; #endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 87362dc..c172f37 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -103,23 +103,6 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(&regs->spi_cfg0_reg, - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - - write32(&regs->spi_cfg2_reg, - ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - - clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h index 034fa35..db3ba21 100644 --- a/src/soc/mediatek/mt8192/include/soc/spi.h +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -7,38 +7,17 @@ #define SPI_BUS_NUMBER 8 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; - uint32_t spi_cfg2_reg; - uint32_t spi_tx_src_64_reg; - uint32_t spi_rx_dst_64_reg; -} mtk_spi_regs; +#define GET_SCK_REG(x) x->spi_cfg2_reg -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) -enum { - SPI_CFG0_CS_HOLD_SHIFT = 0, - SPI_CFG0_CS_SETUP_SHIFT = 16, -}; +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) -enum { - SPI_CFG2_SCK_LOW_SHIFT = 0, - SPI_CFG2_SCK_HIGH_SHIFT = 16, -}; - -enum { - SPI_CFG1_TICK_DLY_SHIFT = 29, - SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, -}; +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c index f7a8756..b5abc85 100644 --- a/src/soc/mediatek/mt8192/spi.c +++ b/src/soc/mediatek/mt8192/spi.c @@ -112,23 +112,6 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(&regs->spi_cfg0_reg, - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - - write32(&regs->spi_cfg2_reg, - ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - - clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, -- To view, visit https://review.coreboot.org/c/coreboot/+/52854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Gerrit-Change-Number: 52854 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Add SPI driver support
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52669 to look at the new patch set (#7). Change subject: soc/mediatek/mt8195: Add SPI driver support ...................................................................... soc/mediatek/mt8195: Add SPI driver support Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang(a)mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/pll.h M src/soc/mediatek/mt8195/include/soc/spi.h M src/soc/mediatek/mt8195/spi.c 4 files changed, 114 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/52669/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Gerrit-Change-Number: 52669 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Fix the FSP_T position
by Arthur Heymans (Code Review) 03 May '21

03 May '21

Attention is currently required from: Paul Menzel, Andrey Petrov, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52850 ) Change subject: drivers/intel/fsp2_0: Fix the FSP_T position ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/52850/comment/a363854e_6fbdf6c8 PS2, Line 81: The location for FSP-T. > Maybe extend and explain, when this needs to be changed, and how the value can be determined? cbfstool relocates this. I'll explain it more in depth. -- To view, visit https://review.coreboot.org/c/coreboot/+/52850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Gerrit-Change-Number: 52850 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 May 2021 11:52:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Fix the FSP_T position
by Paul Menzel (Code Review) 03 May '21

03 May '21

Attention is currently required from: Arthur Heymans, Andrey Petrov, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52850 ) Change subject: drivers/intel/fsp2_0: Fix the FSP_T position ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52850/comment/95fa480c_0a76896b PS2, Line 7: FSP_T FSP-T as below? File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/52850/comment/4f10485a_e8cd16c8 PS2, Line 81: The location for FSP-T. Maybe extend and explain, when this needs to be changed, and how the value can be determined? -- To view, visit https://review.coreboot.org/c/coreboot/+/52850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Gerrit-Change-Number: 52850 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 May 2021 11:37:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/vboot: Include fspt.bin in the RO region only
by Arthur Heymans (Code Review) 03 May '21

03 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52853 ) Change subject: security/vboot: Include fspt.bin in the RO region only ...................................................................... security/vboot: Include fspt.bin in the RO region only fspt.bin is run before verstage so it is of no use in RW_A/B. Change-Id: I6fe29793fa638312c8b275b6fa8662df78b3b2bd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/vboot/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/52853/1 diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index cecaa2d..668d3d9 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -187,6 +187,7 @@ cmos.default \ intel_fit \ intel_fit_ts \ + fspt.bin \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ ,$(1)),COREBOOT,\ $(if $(filter \ -- To view, visit https://review.coreboot.org/c/coreboot/+/52853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fe29793fa638312c8b275b6fa8662df78b3b2bd Gerrit-Change-Number: 52853 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
by Maulik V Vaghela (Code Review) 03 May '21

03 May '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Tim Wawrzynczak, Sugnan Prabhu S, Bernardo Perez Priego, Ronak Kanabar. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52270 ) Change subject: mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... Patch Set 11: (1 comment) File src/mainboard/intel/adlrvp/early_gpio.c: https://review.coreboot.org/c/coreboot/+/52270/comment/d345a68c_1cec178b PS10, Line 20: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), > May I ask where these mappings come from? It's slightly curious that there's 16 in a row then a big […] Hi Tim, The mapping is like this for each port because of Tx-Rx lines of PCI port. We have 0-15 as Tx and 64-67 as Rx for port 0 and thus we configure it in that sequence. -- To view, visit https://review.coreboot.org/c/coreboot/+/52270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1 Gerrit-Change-Number: 52270 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 May 2021 10:19:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/tpm/crtm: Measure FMAP into TPM
by Patrick Rudolph (Code Review) 03 May '21

03 May '21

Attention is currently required from: Philipp Deppenwiese, Julius Werner, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52753 ) Change subject: security/tpm/crtm: Measure FMAP into TPM ...................................................................... Patch Set 2: (1 comment) File src/security/tpm/tspi/crtm.c: https://review.coreboot.org/c/coreboot/+/52753/comment/7ce24fef_bc49e9b3 PS2, Line 64: TPM_CRTM_PCR why doesn't it use TPM_RUNTIME_DATA_PCR? -- To view, visit https://review.coreboot.org/c/coreboot/+/52753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic424a094e7f790cce45c5a98b8bc6d46a8dcca1b Gerrit-Change-Number: 52753 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 03 May 2021 10:04:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021