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Change subject: drivers/genesyslogic/gl9755: Disable the debug mode of short circuit protection
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Hi Tim, I don't mind updating the msg. Please tell me your opinion.
Like Paul suggested here: https://review.coreboot.org/c/coreboot/+/51000/comment/0a885abf_26815c8e/
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Change subject: security/vboot: Include fspt.bin in the RO region only
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Does having the ACPI code do any harm?
My guess is not as long as the code is bound to the existence of a probeable device. However, if the SD controller is in ACPI mode there is no probing aside from ACPI so it might be doing accesses to addresses that are invalid. I haven't inspected anything along those lines though.
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Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> On some devices the native SD controller was not utilized. A USB-to-SD controller was used instead. […]
Does having the ACPI code do any harm?
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Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Can somebody check why this was added? CB:12946, BUG=chrome-os-partner:48190 […]
On some devices the native SD controller was not utilized. A USB-to-SD controller was used instead. Reading through the bug, it seems the intent was to drop the code needing to interact with the device as it was expected to be turned off.
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Change subject: mb/amd/majolica:Set S0i3 enabled by default
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/amd/majolica/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/52857/comment/2b8571fd_a0723db2
PS1, Line 79: register
> Can you add this above next to the other register definition.
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt Papageorge, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/amd/majolica:Set S0i3 enabled by default
......................................................................
mb/amd/majolica:Set S0i3 enabled by default
Set enable S0i3 for Majolica.
BUG=178728116
TEST=Cold boot and perform a cycle of S0i3.
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c
---
M src/mainboard/amd/majolica/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/52857/2
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Hello build bot (Jenkins), EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/mancomb: Fix S0i3/S3 GPIO configuration
......................................................................
mb/google/mancomb: Fix S0i3/S3 GPIO configuration
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.
BUG=b:186011392
TEST=none
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ib956fc299fe21cd7ea0b465cbdc5c8da830a668d
---
M src/mainboard/google/mancomb/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/52802/2
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Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52737 )
Change subject: libpayload: i8042: Enable keyboard translation by default on exit
......................................................................
libpayload: i8042: Enable keyboard translation by default on exit
Add a Kconfig option to set the keyboard translation state on exit and
set the default to true. This restores the keyboard to the power-up
defaults for firmware that does not always run libpayload keyboard init
to have consistent state, and provides an option to disable translation
for keyboards that might need it.
Change-Id: I25dfe3f425a5bb57e97476564886672b707aa3bd
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52737
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
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Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/drivers/i8042/keyboard.c
2 files changed, 6 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Furquan Shaikh: Looks good to me, approved
Felix Singer: Looks good to me, but someone else must approve
Raul Rangel: Looks good to me, approved
Angel Pons: Looks good to me, but someone else must approve
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 7a502b5..f7d78e0 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -385,6 +385,11 @@
depends on PC_KEYBOARD
default n
+config PC_KEYBOARD_TRANSLATION
+ bool "Enable or Disable translation in PC keyboard set 2 on exit"
+ depends on PC_KEYBOARD
+ default y
+
endmenu
menu "Drivers"
diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c
index a695723..952f5f1 100644
--- a/payloads/libpayload/drivers/i8042/keyboard.c
+++ b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -658,7 +658,7 @@
/* Nobody but us seems to still use scancode set #1.
So try to hand over with more modern settings. */
set_scancode_set(2);
- i8042_set_kbd_translation(false);
+ i8042_set_kbd_translation(CONFIG(LP_PC_KEYBOARD_TRANSLATION));
/* Send keyboard disconnect command */
i8042_cmd(I8042_CMD_DIS_KB);
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