coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/cezanne: Publish _LPI
by Jason Glenesk (Code Review) 04 May '21

04 May '21

Jason Glenesk has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52381 ) Change subject: soc/amd/cezanne: Publish _LPI ...................................................................... Abandoned placed by other cl -- To view, visit https://review.coreboot.org/c/coreboot/+/52381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f21f55827b04ee8bb07240bcbec71bd6927c9e Gerrit-Change-Number: 52381 Gerrit-PatchSet: 6 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/cezanne: Publish upep device when modern standby enabled
by Jason Glenesk (Code Review) 04 May '21

04 May '21

Jason Glenesk has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52043 ) Change subject: soc/amd/cezanne: Publish upep device when modern standby enabled ...................................................................... Abandoned placed by other cl -- To view, visit https://review.coreboot.org/c/coreboot/+/52043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib417afebe0dfbb950a7570878dcaefc01e2fbc9f Gerrit-Change-Number: 52043 Gerrit-PatchSet: 7 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: acpi: Add support to generate upep structure
by Jason Glenesk (Code Review) 04 May '21

04 May '21

Jason Glenesk has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52037 ) Change subject: acpi: Add support to generate upep structure ...................................................................... Abandoned placed by other cl -- To view, visit https://review.coreboot.org/c/coreboot/+/52037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b64ddc9ebee251f3b50e81374c1b32cf5b1aeca Gerrit-Change-Number: 52037 Gerrit-PatchSet: 6 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/guybrush: Fix S0i3/S3 GPIO configuration
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian. Hello build bot (Jenkins), Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52801 to look at the new patch set (#2). Change subject: mb/google/guybrush: Fix S0i3/S3 GPIO configuration ...................................................................... mb/google/guybrush: Fix S0i3/S3 GPIO configuration Using PAD_WAKE is actually wrong. The wake bits are only supposed to be set when using the GPIO controller to wake the system. Coreboot's current architecture relies on using GPEs to wake the system. BUG=b:186011392 TEST=Wake system from S0i3 with EC and see GPE 3 increment. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/52801/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c Gerrit-Change-Number: 52801 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/amd/majolica: Add Majolica mainboard specific upep support
by Jason Glenesk (Code Review) 04 May '21

04 May '21

Jason Glenesk has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52039 ) Change subject: mainboard/amd/majolica: Add Majolica mainboard specific upep support ...................................................................... Abandoned placed by other cl -- To view, visit https://review.coreboot.org/c/coreboot/+/52039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If360242e14e29b28a5c03fab3dc2423b086c57d0 Gerrit-Change-Number: 52039 Gerrit-PatchSet: 6 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52808 ) Change subject: soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros ...................................................................... soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros The usage of `pci_devfn_t` here is misleading, as these intentionally store the `PCH_DEVFN_*` macros so they can be used across `smm` and `ramstage` without requiring the device model. Update to `unsigned int` instead, as `pci_devfn_t` implies the data is an MMCONF-compatible PCI devfn offset. Change-Id: Ic8880de984e6eceda4cbe141e118f3a5fdd672a2 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52808 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/elog.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/skylake/elog.c M src/soc/intel/tigerlake/elog.c 4 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 84765d9..7b0fd87 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -12,7 +12,7 @@ #include <types.h> struct pme_map { - pci_devfn_t devfn; + unsigned int devfn; unsigned int wake_source; }; diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 858b371..61b8fb8 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -12,7 +12,7 @@ #include <types.h> struct pme_map { - pci_devfn_t devfn; + unsigned int devfn; unsigned int wake_source; }; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index c6be670..1c80517 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -26,7 +26,7 @@ } struct pme_status_info { - pci_devfn_t devfn; + unsigned int devfn; uint8_t reg_offset; uint32_t elog_event; }; diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 0fccf84..93174be 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -12,7 +12,7 @@ #include <types.h> struct pme_map { - pci_devfn_t devfn; + unsigned int devfn; unsigned int wake_source; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8880de984e6eceda4cbe141e118f3a5fdd672a2 Gerrit-Change-Number: 52808 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device: Switch pci_dev_is_wake_source to take pci_devfn_t
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52765 ) Change subject: device: Switch pci_dev_is_wake_source to take pci_devfn_t ...................................................................... device: Switch pci_dev_is_wake_source to take pci_devfn_t With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/device/pci_ops.c M src/drivers/wifi/generic/generic.c M src/include/device/pci_ops.h M src/soc/intel/alderlake/elog.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/tigerlake/elog.c 6 files changed, 25 insertions(+), 59 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index aaa9f95..76d5e96 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -79,19 +79,16 @@ die("PCI: dev is NULL!\n"); } -bool pci_dev_is_wake_source(const struct device *dev) +bool pci_dev_is_wake_source(pci_devfn_t dev) { unsigned int pm_cap; uint16_t pmcs; - if (dev->path.type != DEVICE_PATH_PCI) - return false; - - pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM); if (!pm_cap) return false; - pmcs = pci_s_read_config16(PCI_BDF(dev), pm_cap + PCI_PM_CTRL); + pmcs = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL); /* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */ return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS); diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 5429f6b..1ee7ab2 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -10,7 +10,7 @@ static void wifi_pci_dev_init(struct device *dev) { - if (pci_dev_is_wake_source(dev)) + if (pci_dev_is_wake_source(PCI_BDF(dev))) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); } diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 7fe7d42..a167825 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -215,6 +215,6 @@ * * Returns true if PCI device is wake source, false otherwise. */ -bool pci_dev_is_wake_source(const struct device *dev); +bool pci_dev_is_wake_source(pci_devfn_t dev); #endif /* PCI_OPS_H */ diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 1efba25..84765d9 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -48,11 +48,8 @@ }; for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { - const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(pme_map[i].devfn), + PCI_FUNC(pme_map[i].devfn)))) elog_add_event_wake(pme_map[i].wake_source, 0); } } @@ -77,11 +74,8 @@ size_t i; for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { - const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) { + unsigned int devfn = ipme_map[i].devfn; + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { elog_add_event_wake(ipme_map[i].wake_source, 0); dev_found = true; } @@ -89,11 +83,8 @@ /* Check Thunderbolt ports */ for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) { + unsigned int devfn = SA_DEVFN_TBT(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); dev_found = true; } @@ -101,11 +92,8 @@ /* Check DMA devices */ for (i = 0; i < NUM_TCSS_DMA_FUNCTIONS; i++) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA(i)); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) { + unsigned int devfn = SA_DEVFN_TCSS_DMA(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TCSS_DMA, i); dev_found = true; } diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index ccf6fd0..858b371 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -48,11 +48,8 @@ }; for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { - const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(pme_map[i].devfn), + PCI_FUNC(pme_map[i].devfn)))) elog_add_event_wake(pme_map[i].wake_source, 0); } } @@ -75,11 +72,8 @@ }; for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { - const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) { + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(ipme_map[i].devfn), + PCI_FUNC(ipme_map[i].devfn)))) { elog_add_event_wake(ipme_map[i].wake_source, 0); dev_found = true; } diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 878959a..0fccf84 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -48,11 +48,8 @@ }; for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { - const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(pme_map[i].devfn), + PCI_FUNC(pme_map[i].devfn)))) elog_add_event_wake(pme_map[i].wake_source, 0); } } @@ -76,12 +73,8 @@ size_t i; for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { - const struct device *dev = - pcidev_path_on_root(ipme_map[i].devfn); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) { + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(ipme_map[i].devfn), + PCI_FUNC(ipme_map[i].devfn)))) { elog_add_event_wake(ipme_map[i].wake_source, 0); dev_found = true; } @@ -89,11 +82,8 @@ /* Check Thunderbolt ports */ for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) { + const unsigned int devfn = SA_DEVFN_TBT(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); dev_found = true; } @@ -101,11 +91,8 @@ /* Check DMA devices */ for (i = 0; i < NUM_TCSS_DMA_FUNCTIONS; i++) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA(i)); - if (!dev) - continue; - - if (pci_dev_is_wake_source(dev)) { + const unsigned int devfn = SA_DEVFN_TCSS_DMA(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TCSS_DMA, i); dev_found = true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Gerrit-Change-Number: 52765 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86: Fix building with CONFIG_VBOOT_SEPARATE_VERSTAGE=n
by Aaron Durbin (Code Review) 04 May '21

04 May '21

Attention is currently required from: Patrick Rudolph, Angel Pons, Arthur Heymans. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52784 ) Change subject: arch/x86: Fix building with CONFIG_VBOOT_SEPARATE_VERSTAGE=n ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1227feab9ffbbc06e614f297be44fb67f13bda42 Gerrit-Change-Number: 52784 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 03 May 2021 16:25:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica:Set S0i3 enabled by default
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt Papageorge, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52857 ) Change subject: mb/amd/majolica:Set S0i3 enabled by default ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Gerrit-Change-Number: 52857 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 03 May 2021 16:23:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Fix S0i3/S3 GPIO configuration
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52801 ) Change subject: mb/google/guybrush: Fix S0i3/S3 GPIO configuration ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/52801/comment/0afab0c3_725aaabb PS1, Line 20: PAD_SCI > I think we might have to use GPIO-controller wake route for the pen eject if we need to apply deboun […] Interesting. Thanks for pointing that out. I think we need to set this to PAD_GPI instead and make it so the kernel driver can set the wake bits. https://lore.kernel.org/patchwork/patch/1420135/ On my device I don't have the PEN plugged in. I've seen that sometimes when I touch the board the PEN glitches a bit and latches the wake_status bit. Since the OS doesn't have a driver loaded for this, the IRQ never gets enabled, so the wake_status never gets cleared. This results in not being able to stay in S0i3. -- To view, visit https://review.coreboot.org/c/coreboot/+/52801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c Gerrit-Change-Number: 52801 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 May 2021 16:22:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021