coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel: Don't select VBOOT_SEPARATE_VERSTAGE
by Arthur Heymans (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Julius Werner, Arthur Heymans, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52788 ) Change subject: soc/intel: Don't select VBOOT_SEPARATE_VERSTAGE ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > +1 to all Furquan said. Linking into bootblock should be more efficient on XIP devices with no other restrictions. > > Have you actually tested this on a board? I seem to recall that once upon a time I found this broken on x86. Don't remember any details though, may well be fixed at this point. I tested on qemu. I'll run a test on a board. -- To view, visit https://review.coreboot.org/c/coreboot/+/52788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525 Gerrit-Change-Number: 52788 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 06:12:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/generic: Set S0W to D3hot for wake device
by Tony Huang (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Tony Huang, Keith Tzeng, Wisley Chen. Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Edward O'Callaghan, Keith Tzeng, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52847 to look at the new patch set (#7). Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device ...................................................................... drivers/i2c/generic: Set S0W to D3hot for wake device If device is supported as a wake source, _S0W should be set to D3hot. This ensures that the device is put into D3hot by the OSPM. Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM. The devices we are currently looking at for touchscreen/touchpad do not really support auxiliary power and so do not support wake from D3cold. BUG=b:186070097 TEST=build and check device wake state _S0W set to 3 in ssdt table. Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M Documentation/acpi/devicetree.md M src/drivers/i2c/generic/generic.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52847/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Gerrit-Change-Number: 52847 Gerrit-PatchSet: 7 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/generic: Set S0W to D3hot for wake device
by Tony Huang (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Keith Tzeng, Wisley Chen. Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Edward O'Callaghan, Keith Tzeng, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52847 to look at the new patch set (#6). Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device ...................................................................... drivers/i2c/generic: Set S0W to D3hot for wake device If device is supported as a wake source, _S0W should be set to D3hot. This ensures that the device is put into D3hot by the OSPM. Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM. The devices we are currently looking at for touchscreen/touchpad do not really support auxiliary power and so do not support wake from D3cold. BUG=b:186070097 TEST=build and check device wake state _S0W set to 3 in ssdt table. Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M Documentation/acpi/devicetree.md M src/drivers/i2c/generic/generic.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52847/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Gerrit-Change-Number: 52847 Gerrit-PatchSet: 6 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/generic: Set S0W to D3hot for wake device
by Tony Huang (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Keith Tzeng, Wisley Chen. Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52847 ) Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52847/comment/c5818317_1a0bccfe PS4, Line 11: The power resource is not turned off. : Hence, it still is capable of waking. > Can you please rephrase this as follows: […] Done Patchset: PS5: Please help review. Thanks File src/drivers/i2c/generic/generic.c: https://review.coreboot.org/c/coreboot/+/52847/comment/521cabc4_0ead582a PS4, Line 101: 3 > ACPI_DEVICE_SLEEP_D3_HOT Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Gerrit-Change-Number: 52847 Gerrit-PatchSet: 5 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 May 2021 06:06:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/generic: Set S0W to D3hot for wake device
by Tony Huang (Code Review) 04 May '21

04 May '21

Attention is currently required from: Tony Huang, Keith Tzeng, Wisley Chen. Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Edward O'Callaghan, Keith Tzeng, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52847 to look at the new patch set (#5). Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device ...................................................................... drivers/i2c/generic: Set S0W to D3hot for wake device If device is supported as a wake source, _S0W should be set to D3hot. This ensures that the device is put into D3hot by the OSPM. Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM. The devices we are currently looking at for touchscreen/touchpad do not really support auxiliary power and so do not support wake from D3cold. BUG=b:186070097 TEST=build and check device wake state _S0W set to 3 in ssdt table. Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M Documentation/acpi/devicetree.md M src/drivers/i2c/generic/generic.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52847/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Gerrit-Change-Number: 52847 Gerrit-PatchSet: 5 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Enable DPTF functionality for Brya
by Sumeet R Pawnikar (Code Review) 04 May '21

04 May '21

Attention is currently required from: John Su. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52691 ) Change subject: mb/google/brya: Enable DPTF functionality for Brya ...................................................................... Patch Set 2: (3 comments) This change is ready for review. File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52691/comment/786a7b20_28b1007f PS2, Line 7: 28, : .tdp_pl2_override = 64 any reference document number for above PL1 and PL2 values? https://review.coreboot.org/c/coreboot/+/52691/comment/51094fd2_8a1bf3c5 PS2, Line 20: tsr[0].desc" = ""Ambient"" : register "options.tsr[1].desc" = ""Battery"" : register "options.tsr[2].desc" = ""DDR"" : register "options.tsr[3].desc" = ""Skin"" I would able to find only 3 sensors as per schematics. Can you please confirm on above sensors on Brya ? https://review.coreboot.org/c/coreboot/+/52691/comment/1c542932_b7e9f0ef PS2, Line 103: It seems all above policy setting values and sensors are the same as https://review.coreboot.org/c/coreboot/+/52020/9/src/mainboard/intel/adlrvp… except PL1 and PL2 power values. -- To view, visit https://review.coreboot.org/c/coreboot/+/52691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I225bc5e5836312a4c1dfabe46ddc5e754f79deb8 Gerrit-Change-Number: 52691 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 May 2021 05:59:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: Enable macronix SPI config
by Shelley Chen (Code Review) 04 May '21

04 May '21

Attention is currently required from: Ravi kumar, Sajida Bhanu, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50583 ) Change subject: herobrine: Enable macronix SPI config ...................................................................... Patch Set 32: -Code-Review (1 comment) Patchset: PS32: > Why Macronix? Are we planning to use that for Herobrine? (This would be the first I heard of us usin […] Ok that's fair. I assumed that QC would know better but didn't verify because I didn't have the I/O board schematics for herobrine yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/50583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Gerrit-Change-Number: 50583 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 04 May 2021 05:23:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add Synology DS918+
by build bot (Jenkins) (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Martin Roth, Angel Pons, Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52594 ) Change subject: mainboard: Add Synology DS918+ ...................................................................... Patch Set 5: (62 comments) File src/mainboard/synology/ds918plus/early_gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/403012f3_5ad9108b PS5, Line 40: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_210, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ1_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/84257adf_93ea2c4b PS5, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/e3428b47_33298f59 PS5, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/1d3fa46f_0b65e28f PS5, Line 60: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART1_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/ffbea76a_d6a6a53a PS5, Line 61: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_TXD */ line over 96 characters File src/mainboard/synology/ds918plus/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/5fdca146_6da29fd8 PS5, Line 47: PAD_CFG_GPI_APIC_IOS(GPIO_33, DN_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/69d2c648_b4d81684 PS5, Line 52: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/34512065_8348a7c5 PS5, Line 53: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/5a120af9_bee7258c PS5, Line 54: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_RTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/43559f94_dd82af51 PS5, Line 55: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_CTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/8aa138fe_88ff8ff6 PS5, Line 56: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART1_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/fb3c88be_8ae69aea PS5, Line 57: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/3eb8376b_dcdd463f PS5, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART1_RTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/667c4bed_5474f679 PS5, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_CTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/e3b1989b_df03ffa5 PS5, Line 85: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/f9b7d4ac_862c4184 PS5, Line 86: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_RSP, DN_20K, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/861c8761_915ea221 PS5, Line 102: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_193, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/0cf1318c_6ea8ac89 PS5, Line 103: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_194, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/7338a7c0_e51b2f79 PS5, Line 104: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_195, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/126a2b47_0dd5323a PS5, Line 114: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_FS0, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/8de79f46_3489ce7f PS5, Line 115: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_FS1, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/8f11b95e_d1462f59 PS5, Line 117: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_RXD, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/c574cbca_073bb761 PS5, Line 118: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_TXD, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/c4954129_4b3dd9d2 PS5, Line 119: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_CLK, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/a3cdceab_adf4102a PS5, Line 121: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_RESET_B, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/0aa66d28_17a3944d PS5, Line 126: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_STDBY, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/aecc9df3_5fa2199c PS5, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_81, DN_20K, DEEP, NF2, TxDRxE, ENPD), /* AVS_I2C4_SDI */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/ad224c59_b45772e8 PS5, Line 139: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_83, DN_20K, DEEP, NF1, TxDRxE, ENPD), /* AVS_DMIC_DATA_2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/5e6442a8_9f3f6cc1 PS5, Line 147: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_91, DN_20K, DEEP, NF1, TxDRxE, ENPD), /* AVS_I2S3_SDI */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/d388768a_7c9ed749 PS5, Line 157: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_CLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/190325fe_bebe1cec PS5, Line 158: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_FS0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/ff75fd66_27dce55f PS5, Line 159: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_FS1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/fc71e770_80f555be PS5, Line 160: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/38f65f22_759c6d6c PS5, Line 161: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/25d5c249_24695232 PS5, Line 177: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/211e9bee_661bce7d PS5, Line 178: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/6509a14b_7817e184 PS5, Line 179: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/fb6aed08_cc26a0f7 PS5, Line 180: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/98aace51_b5c34aa9 PS5, Line 181: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C2_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/eb492ae8_e558732a PS5, Line 182: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C2_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/23a9be65_34e2c7a5 PS5, Line 183: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C3_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/97779d9c_05b20132 PS5, Line 184: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C3_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/ef58b576_d51e360b PS5, Line 185: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C4_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/8a407618_e76be13a PS5, Line 186: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C4_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/125b8ea9_7dbc9402 PS5, Line 187: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_134, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/261ef5e0_70928201 PS5, Line 188: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_135, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/10c3ab40_6e922019 PS5, Line 189: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_136, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/e88be9b7_7ce8251d PS5, Line 190: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_137, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/0609d706_c63783fe PS5, Line 191: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), /* LPSS_I2C7_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/fcc4d5be_cd3e184d PS5, Line 192: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), /* LPSS_I2C7_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/58fed6c3_0d7158b5 PS5, Line 203: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ0_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/47378baa_0049c0dd PS5, Line 204: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_210, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ1_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/7bf11018_97c59da4 PS5, Line 205: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ2_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/eda965c6_53264d74 PS5, Line 206: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_212, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ3_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/294ae92d_ada5804f PS5, Line 216: PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/5796b494_1515125d PS5, Line 221: PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 1, DEEP, UP_20K, IGNORE, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/9c9e17eb_504cc45b PS5, Line 264: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/004883c3_9c71c374 PS5, Line 265: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/d899f061_613c3f5b PS5, Line 266: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/728998ec_a402d434 PS5, Line 267: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/8f3aec22_4b88c57f PS5, Line 268: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118329): https://review.coreboot.org/c/coreboot/+/52594/comment/bcde9307_0f6e11a4 PS5, Line 270: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_FRAMEB */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Gerrit-Change-Number: 52594 Gerrit-PatchSet: 5 Gerrit-Owner: Name of user not set #1003506 Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 04 May 2021 05:06:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add Synology DS918+
by Name of user not set (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Martin Roth, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52594 to look at the new patch set (#5). Change subject: mainboard: Add Synology DS918+ ...................................................................... mainboard: Add Synology DS918+ I'm new to coreboot. This port is based on 4.13, this board boots. Tested with tianocore. Can provide serial logs, original Synology's DSM OS works fine with this port. Can run tests on my board. Now works on Master. Things todo: * polish * I211 ethernet chips don't work in OS * 2nd HSUART Serial doesn't work in OS, only in original DSM. Tried all console=ttyS*,115200 and all 'set tty com*' (as per obsd), probably not cb problem. * Freebsd usb stick causes X86 exception, OpenBSD fails to boot at entry point 0x1001000. Both have apl support. log: https://clbin.com/JrurJ * ... Patch set 2 Reformated gpio part and dsdt. Here are serial logs: https://clbin.com/tHOE7 -- Master branch https://clbin.com/wp4R8 -- 4.13 + seabios, same code except 1 include in dsdt https://clbin.com/iUrgJ -- 4.13 + tianocore, same code... Video test: https://schizoden.xyz/videos/watch/816c5a68-af6f-4dd4-8c7e-43d068410822 Patch set 3/4 More gpio reformating, added data.vbt from vendors bios. * trim spare lines on the end, for jenkins sake Patch set 5 Removed data.vbt, causes serial to shut off at post 0x98 Fixed cbfs>mem-mapped area from ifwi + MCACHE -400 err -- .fmd Added cmos.layout cmos.default Edited pci-e devices and turned on vtd in devicetree.cb Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Signed-off-by: mkjOoB <dump(a)schizoden.xyz> --- A src/mainboard/synology/Kconfig A src/mainboard/synology/Kconfig.name A src/mainboard/synology/ds918plus/Kconfig A src/mainboard/synology/ds918plus/Kconfig.name A src/mainboard/synology/ds918plus/Makefile.inc A src/mainboard/synology/ds918plus/board_info.txt A src/mainboard/synology/ds918plus/bootblock.c A src/mainboard/synology/ds918plus/cmos.default A src/mainboard/synology/ds918plus/cmos.layout A src/mainboard/synology/ds918plus/devicetree.cb A src/mainboard/synology/ds918plus/ds918plus.fmd A src/mainboard/synology/ds918plus/dsdt.asl A src/mainboard/synology/ds918plus/early_gpio.c A src/mainboard/synology/ds918plus/gpio.c A src/mainboard/synology/ds918plus/gpio.h A src/mainboard/synology/ds918plus/mainboard.c A src/mainboard/synology/ds918plus/romstage.c 17 files changed, 642 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52594/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Gerrit-Change-Number: 52594 Gerrit-PatchSet: 5 Gerrit-Owner: Name of user not set #1003506 Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO
by Maulik V Vaghela (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52783 ) Change subject: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52783/comment/49d98781_e43a4ade PS5, Line 11: ,c > nit: space after comma Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d Gerrit-Change-Number: 52783 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 04:52:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit May 2021