coreboot-gerrit May 2021

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Change in coreboot[master]: soc/mediatek/mt8195: add pmif/spmi/pmic driver
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52668 ) Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8195/pmif_clk.c: https://review.coreboot.org/c/coreboot/+/52668/comment/54ad113b_7c7dc31f PS7, Line 115: __func__ > Please align with BIOS_ERROR Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Gerrit-Change-Number: 52668 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 04 May 2021 02:25:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add SPI driver support
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52669 to look at the new patch set (#11). Change subject: soc/mediatek/mt8195: Add SPI driver support ...................................................................... soc/mediatek/mt8195: Add SPI driver support Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang(a)mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/pll.h M src/soc/mediatek/mt8195/include/soc/spi.h M src/soc/mediatek/mt8195/spi.c 4 files changed, 114 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/52669/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/52669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Gerrit-Change-Number: 52669 Gerrit-PatchSet: 11 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: add pmif/spmi/pmic driver
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52668 to look at the new patch set (#8). Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver ...................................................................... soc/mediatek/mt8195: add pmif/spmi/pmic driver MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen(a)mediatek.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/pmif_spmi.h M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/iocfg.h A src/soc/mediatek/mt8195/include/soc/pmif.h A src/soc/mediatek/mt8195/mt6315.c A src/soc/mediatek/mt8195/mt6359p.c A src/soc/mediatek/mt8195/pmif_clk.c A src/soc/mediatek/mt8195/pmif_spi.c A src/soc/mediatek/mt8195/pmif_spmi.c 10 files changed, 927 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/52668/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Gerrit-Change-Number: 52668 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Add NOR-Flash support
by Yu-Ping Wu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52872 ) Change subject: mb/google/cherry: Add NOR-Flash support ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/cherry/bootblock.c: PS1: Similar to Patrick's comment in CB:52668, could you split this into two patches: one for soc and the other for mainboard? File src/soc/mediatek/mt8195/include/soc/symbols.h: https://review.coreboot.org/c/coreboot/+/52872/comment/cedb6930_6c7ad605 PS1, Line 9: 2 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I356e6b1cba3c078bf99e056b290476c7179e8ccf Gerrit-Change-Number: 52872 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 04 May 2021 02:13:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/genesyslogic/gl9755: Disable debug mode to enable circuit pro...
by Ben Chuang (Code Review) 03 May '21

03 May '21

Attention is currently required from: Paul Menzel, Zhuohao Lee. Ben Chuang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51000 ) Change subject: drivers/genesyslogic/gl9755: Disable debug mode to enable circuit protections ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51000/comment/72239a62_dffbbb06 PS1, Line 7: Disable the debug mode of short circuit protection > > Disable debug mode to enable circuit protections Done Patchset: PS2: > Like Paul suggested here: https://review.coreboot. […] Updated it. Thanks for reminding. -- To view, visit https://review.coreboot.org/c/coreboot/+/51000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacfa3c668a52d1bae15fe82f1c614d0ebd93a957 Gerrit-Change-Number: 51000 Gerrit-PatchSet: 3 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Greg Tu <greg.tu(a)genesyslogic.com.tw> Gerrit-CC: HsuanYang Chen <ynop77(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: 陳建宏 <renius.chen(a)genesyslogic.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 02:11:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ben Chuang <benchuanggli(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add SPI driver support
by Yu-Ping Wu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52669 ) Change subject: soc/mediatek/mt8195: Add SPI driver support ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/mt8195/spi.c: https://review.coreboot.org/c/coreboot/+/52669/comment/c0acd9ce_8a3cae7b PS10, Line 4: #include <assert.h> Sort -- To view, visit https://review.coreboot.org/c/coreboot/+/52669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Gerrit-Change-Number: 52669 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 May 2021 02:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: add pmif/spmi/pmic driver
by Yu-Ping Wu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52668 ) Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver ...................................................................... Patch Set 7: (2 comments) File src/soc/mediatek/mt8195/pmif_clk.c: PS3: > Maybe at least we can extract pmif_ulposc_cali() to a common file, since the binary search should be […] ping? File src/soc/mediatek/mt8195/pmif_clk.c: https://review.coreboot.org/c/coreboot/+/52668/comment/3fb82263_7290328c PS7, Line 115: __func__ Please align with BIOS_ERROR -- To view, visit https://review.coreboot.org/c/coreboot/+/52668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Gerrit-Change-Number: 52668 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 04 May 2021 02:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Move the common part of SPI drivers to common/
by Yu-Ping Wu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52854 ) Change subject: soc/mediatek: Move the common part of SPI drivers to common/ ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Gerrit-Change-Number: 52854 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 04 May 2021 02:04:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT
by Kane Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Hello Kane Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52874 to review the following change. Change subject: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT ...................................................................... soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT On tgl, we noticed system hang if a shutdown is triggered before fsps. The dut is unable to shutdown properly due to tcss is stuck before tcss_init in fsps. This change enable power button smi on jsl, tgl, adl after fsps. it can also prevent a shutdown failure due to lack of fsps init on certain ip. Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pmc.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/pmc.c 6 files changed, 38 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/52874/1 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 6de1cb0..7bc72e1 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -102,7 +102,7 @@ * Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - global_smi_enable(); + global_smi_enable_no_pwrbtn(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index e4c1009..69477f7 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -18,6 +18,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <stdint.h> +#include <bootstate.h> #define PMC_HID "INTC1026" @@ -141,6 +142,17 @@ pmc_set_acpi_mode(); } +static void pm1_enable_pwrbtn_smi(void *unused) +{ + /* + * Enable Power button SMI only after BS_DEV_INIT_CHIPS(FSPS) is done. + */ + pmc_update_pm1_enable(PWRBTN_EN); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); + + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 8e54eaa..924aa3c 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -96,7 +96,7 @@ * Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - global_smi_enable(); + global_smi_enable_no_pwrbtn(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index c0507d6..fcbe024 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -93,6 +93,17 @@ pmc_set_acpi_mode(); } +static void pm1_enable_pwrbtn_smi(void *unused) +{ + /* + * Enable Power button SMI only after BS_DEV_INIT_CHIPS(FSPS) is done. + */ + pmc_update_pm1_enable(PWRBTN_EN); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); + + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 925bddb..e313cce 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -102,7 +102,7 @@ * Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - global_smi_enable(); + global_smi_enable_no_pwrbtn(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index c5a4ae5..124ee65 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -18,6 +18,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <bootstate.h> #define PMC_HID "INTC1026" @@ -145,6 +146,17 @@ pmc_set_acpi_mode(); } +static void pm1_enable_pwrbtn_smi(void *unused) +{ + /* + * Enable Power button SMI only after BS_DEV_INIT_CHIPS(FSPS) is done. + */ + pmc_update_pm1_enable(PWRBTN_EN); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); + + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/52874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Gerrit-Change-Number: 52874 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{adl, tgl, jsl}: skip bus master disable on PMC device
by Kane Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Kane Chen. Hello Kane Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52873 to review the following change. Change subject: soc/intel/{adl, tgl, jsl}: skip bus master disable on PMC device ...................................................................... soc/intel/{adl, tgl, jsl}: skip bus master disable on PMC device We found system hang if the shutdown is triggered before fsps. This is due to the io decode enable on pmc is disabled by busmaster_disable_on_bus function. Hence, the slp_en on acpi pm1_cnt register doesn't succeed. So this change skip pmc bus disable before shutdown. The reason issue is not reproduced after fsps is beacause pmc pci device is hidden after fsps. That's why busmaster_disable_on_bus won't clear io deocde on pmc device. Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c --- M src/soc/intel/alderlake/smihandler.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/52873/1 diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index a072138..661a747 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -24,6 +24,13 @@ heci_disable(); } +int smihandler_soc_disable_busmaster(pci_devfn_t dev) +{ + if (dev == PCH_DEV_PMC) + return 0; + return 1; +} + const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 448c053..9867166 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -24,6 +24,13 @@ heci_disable(); } +int smihandler_soc_disable_busmaster(pci_devfn_t dev) +{ + if (dev == PCH_DEV_PMC) + return 0; + return 1; +} + const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 67d21f8..1389c5b 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -24,6 +24,13 @@ heci_disable(); } +int smihandler_soc_disable_busmaster(pci_devfn_t dev) +{ + if (dev == PCH_DEV_PMC) + return 0; + return 1; +} + const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, -- To view, visit https://review.coreboot.org/c/coreboot/+/52873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Gerrit-Change-Number: 52873 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021