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Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52847/comment/edfa8fed_407da5f0
PS1, Line 9: 3
> Only because this commit impacts many boards can you elaborate a little more why `3` and not `4` to […]
Done
File src/drivers/i2c/generic/generic.c:
https://review.coreboot.org/c/coreboot/+/52847/comment/bacd22dc_942fa54f
PS1, Line 101: 3);
> please update `Documentation/acpi/devicetree.md` as well.
Done
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Deepti Deshatty has uploaded a new patch set (#6) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/50996 )
Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................
mb/adlrvp: Fix DDR5 Boot issue
Currently, DDR5 boot is broken due to reading of spd data
via SMBus through coreboot. This implementation requires study
of spd5 architecture and is currently Work In Progress.
Switching to the older implemention of booting DDR5 by passing
DIMM slave address to FSP through this CL.
BUG=b:180458099
TEST=Boot DDR5 to kernel
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/6
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Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device
......................................................................
Patch Set 8: Code-Review+2
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John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52691 )
Change subject: mb/google/brya: Enable DPTF functionality for Brya
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Patch Set 2:
>
> (3 comments)
>
> This change is ready for review.
Hi Sumeet
Thanks your review.
I just create dptf device tree for byra.
Wait to our thermal team provide correct thermal table.
And I will update CL for review.
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Change subject: mb/google/octopus: add audio codec into SSFC support for Phaser
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/octopus/variants/phaser/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118339):
https://review.coreboot.org/c/coreboot/+/52878/comment/5f30ca32_c08a0fed
PS4, Line 40: PAD_CFG_GPI_APIC_IOS(GPIO_137,NONE, DEEP, LEVEL, INVERT, HIZCRx1,
space required after that ',' (ctx:VxV)
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google/octopus: add audio codec into SSFC support for Phaser
......................................................................
mb/google/octopus: add audio codec into SSFC support for Phaser
Add audio codec module RT5682I in project.
BUG=b:182221327
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one.
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3
---
M src/mainboard/google/octopus/Kconfig.name
M src/mainboard/google/octopus/variants/phaser/gpio.c
M src/mainboard/google/octopus/variants/phaser/overridetree.cb
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/52878/4
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Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/52879 )
Change subject: arch/x86/walkcbfs.S: Use FMAP instead "cbfs master header"
......................................................................
arch/x86/walkcbfs.S: Use FMAP instead "cbfs master header"
Tested on qemu/i440fx on X86_64:
- Page tables are found in cbfs (finding a file works)
- returns 0 when a file is not found
- works when there is no cbfs file at the start of the FMAP, e.g. with
the cbfs master header removed.
Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/walkcbfs.S
1 file changed, 5 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/52879/2
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52626 )
Change subject: mb/google/dedede: Create pirika variant
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Patchset:
PS1:
Other than the comment, it looks good.
File src/mainboard/google/dedede/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/52626/comment/f5abb5da_5b595214
PS1, Line 138: bool "-> Pirika"
Is it based on CR50 or TPM2. Please enable the config accordingly. This used to be enabled by default earlier. But with second sourcing of TPM, we need to enable this explicitly.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/octopus: add audio codec into SSFC support for Phaser
......................................................................
mb/google/octopus: add audio codec into SSFC support for Phaser
Add audio codec module RT5682I in project.
BUG=b:182221327
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one.
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3
---
M src/mainboard/google/octopus/Kconfig.name
M src/mainboard/google/octopus/variants/phaser/gpio.c
M src/mainboard/google/octopus/variants/phaser/overridetree.cb
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/52878/3
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Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Edward O'Callaghan, Keith Tzeng, Wisley Chen,
I'd like you to reexamine a change. Please visit
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Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device
......................................................................
drivers/i2c/generic: Set S0W to D3hot for wake device
If device is supported as a wake source, _S0W should be set to D3hot.
This ensures that the device is put into D3hot by the OSPM.
Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM.
The devices we are currently looking at for touchscreen/touchpad
do not really support auxiliary power and so do not support wake from D3cold.
BUG=b:186070097
TEST=build and check device wake state _S0W set to 3 in ssdt table.
Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M Documentation/acpi/devicetree.md
M src/drivers/i2c/generic/generic.c
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52847/8
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